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[AMDGPU] Add verification for amdgcn.init.exec.from.input #128172
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Check that the input register is an inreg argument to the parent function. (See the comment in `IntrinsicsAMDGPU.td`.) This LLVM defect was identified via the AMD Fuzzing project.
@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-ir Author: Robert Imschweiler (ro-i) ChangesCheck that the input register is an inreg argument to the parent function. (See the comment in This LLVM defect was identified via the AMD Fuzzing project. Full diff: https://github.com/llvm/llvm-project/pull/128172.diff 2 Files Affected:
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 8432779c107de..55923fd56a109 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -6369,6 +6369,21 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
"VGPR arguments must not have the `inreg` attribute", &Call);
break;
}
+ case Intrinsic::amdgcn_init_exec_from_input: {
+ const Value *InputVal = Call.getOperand(0);
+ bool InRegArgFound = false;
+ for (const Argument &Arg : Call.getCaller()->args()) {
+ if (Arg.hasInRegAttr() && &Arg == InputVal) {
+ InRegArgFound = true;
+ break;
+ }
+ }
+ Check(InRegArgFound,
+ "only inreg arguments to the parent function are valid as inputs to "
+ "this intrinsic",
+ &Call);
+ break;
+ }
case Intrinsic::amdgcn_set_inactive_chain_arg: {
auto CallerCC = Call.getCaller()->getCallingConv();
switch (CallerCC) {
diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-init-exec-from-input.ll b/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-init-exec-from-input.ll
new file mode 100644
index 0000000000000..5e4a6638dc170
--- /dev/null
+++ b/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-init-exec-from-input.ll
@@ -0,0 +1,27 @@
+; RUN: sed -e '/^; MARK$/,$d' %s | not llc -mtriple=amdgcn -mcpu=gfx942 2>&1 | FileCheck %s
+; RUN: sed -e '1,/^; MARK$/d' %s | llc -mtriple=amdgcn -mcpu=gfx942 -filetype=null
+
+; Function Attrs: convergent nocallback nofree nounwind willreturn
+declare void @llvm.amdgcn.init.exec.from.input(i32, i32 immarg) #0
+attributes #0 = { convergent nocallback nofree nounwind willreturn }
+
+; CHECK: only inreg arguments to the parent function are valid as inputs to this intrinsic
+; CHECK-NEXT: call void @llvm.amdgcn.init.exec.from.input(i32 0, i32 0)
+define amdgpu_ps void @init_exec_from_input_fail_immarg(i32 inreg %a, i32 %b) {
+ call void @llvm.amdgcn.init.exec.from.input(i32 0, i32 0)
+ ret void
+}
+
+; CHECK: only inreg arguments to the parent function are valid as inputs to this intrinsic
+; CHECK-NEXT: call void @llvm.amdgcn.init.exec.from.input(i32 %b, i32 0)
+define amdgpu_ps void @init_exec_from_input_fail_not_inreg(i32 inreg %a, i32 %b) {
+ call void @llvm.amdgcn.init.exec.from.input(i32 %b, i32 0)
+ ret void
+}
+
+; MARK
+
+define amdgpu_ps void @init_exec_from_input_success(i32 inreg %a, i32 %b) {
+ call void @llvm.amdgcn.init.exec.from.input(i32 %a, i32 0)
+ ret void
+}
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llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-init-exec-from-input.ll
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llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-init-exec-from-input.ll
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@@ -18,10 +17,3 @@ define amdgpu_ps void @init_exec_from_input_fail_not_inreg(i32 inreg %a, i32 %b) | |||
call void @llvm.amdgcn.init.exec.from.input(i32 %b, i32 0) | |||
ret void | |||
} |
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Also test a case where it's not an argument (try one with a constant and one with an instruction)
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Thanks, I added another check for the case that the operand is an instruction!
Isn't the constant case covered by the first function?
llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-init-exec-from-input.ll
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Don't know why we have a separate intrinsic for the case where the value happens to be an argument or not
llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-init-exec-from-input.ll
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/38/builds/2473 Here is the relevant piece of the build log for the reference
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Check that the input register is an inreg argument to the parent function. (See the comment in
IntrinsicsAMDGPU.td
.)This LLVM defect was identified via the AMD Fuzzing project.