[CodeGen] Use Register in SDep interface. NFC

[topperc]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-hexagon

Author: Craig Topper (topperc)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/129734.diff

2 Files Affected:

• (modified) llvm/include/llvm/CodeGen/ScheduleDAG.h (+10-10)
• (modified) llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (+1-1)

diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index 54e65335edf3a..9535c5a99681d 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -101,20 +101,20 @@ class TargetRegisterInfo;
     SDep() : Dep(nullptr, Data) {}
 
     /// Constructs an SDep with the specified values.
-    SDep(SUnit *S, Kind kind, unsigned Reg)
+    SDep(SUnit *S, Kind kind, Register Reg)
       : Dep(S, kind), Contents() {
       switch (kind) {
       default:
         llvm_unreachable("Reg given for non-register dependence!");
       case Anti:
       case Output:
-        assert(Reg != 0 &&
+        assert(Reg &&
                "SDep::Anti and SDep::Output must use a non-zero Reg!");
-        Contents.Reg = Reg;
+        Contents.Reg = Reg.id();
         Latency = 0;
         break;
       case Data:
-        Contents.Reg = Reg;
+        Contents.Reg = Reg.id();
         Latency = 1;
         break;
       }
@@ -209,13 +209,13 @@ class TargetRegisterInfo;
 
     /// Tests if this is a Data dependence that is associated with a register.
     bool isAssignedRegDep() const {
-      return getKind() == Data && Contents.Reg != 0;
+      return getKind() == Data && Contents.Reg;
     }
 
     /// Returns the register associated with this edge. This is only valid on
     /// Data, Anti, and Output edges. On Data edges, this value may be zero,
     /// meaning there is no associated register.
-    unsigned getReg() const {
+    Register getReg() const {
       assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
              "getReg called on non-register dependence edge!");
       return Contents.Reg;
@@ -225,14 +225,14 @@ class TargetRegisterInfo;
     /// Data, Anti, and Output edges. On Anti and Output edges, this value must
     /// not be zero. On Data edges, the value may be zero, which would mean that
     /// no specific register is associated with this edge.
-    void setReg(unsigned Reg) {
+    void setReg(Register Reg) {
       assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
              "setReg called on non-register dependence edge!");
-      assert((getKind() != Anti || Reg != 0) &&
+      assert((getKind() != Anti || Reg) &&
              "SDep::Anti edge cannot use the zero register!");
-      assert((getKind() != Output || Reg != 0) &&
+      assert((getKind() != Output || Reg) &&
              "SDep::Output edge cannot use the zero register!");
-      Contents.Reg = Reg;
+      Contents.Reg = Reg.id();
     }
 
     void dump(const TargetRegisterInfo *TRI = nullptr) const;
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 7f9b9ffc34e7d..7bd392907716c 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -532,7 +532,7 @@ bool HexagonPacketizerList::updateOffset(SUnit *SUI, SUnit *SUJ) {
   // involves the specific register.
   for (const auto &PI : SUI->Preds)
     if (PI.getKind() != SDep::Anti &&
-        (PI.getKind() != SDep::Data || PI.getReg() != Reg))
+        (PI.getKind() != SDep::Data || Register(PI.getReg()) != Reg))
       return false;
   int Incr;
   if (!HII->getIncrementValue(MJ, Incr))

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