[PowerPC] Add intrinsics and tests for basic Dense Math enablement instructions #129913
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@llvm/pr-subscribers-llvm-ir @llvm/pr-subscribers-backend-powerpc Author: None (RolandF77) ChangesAdd intrinsics and tests for Dense Math basic enablement instructions dmsetdmrz, dmmr, dmxor. Full diff: https://github.com/llvm/llvm-project/pull/129913.diff 2 Files Affected:
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 6f49ed39d8a09..af66b8206182e 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1644,6 +1644,16 @@ let TargetPrefix = "ppc" in {
def int_ppc_mma_xxsetaccz :
DefaultAttrsIntrinsic<[llvm_v512i1_ty], [], [IntrNoMem]>;
+ def int_ppc_mma_dmsetdmrz :
+ DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [], [IntrNoMem]>;
+
+ def int_ppc_mma_dmmr :
+ DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty], [IntrNoMem]>;
+
+ def int_ppc_mma_dmxor :
+ DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty,
+ llvm_v1024i1_ty], [IntrNoMem]>;
+
// MMA Reduced-Precision: Outer Product Intrinsic Definitions.
defm int_ppc_mma_xvi4ger8 :
PowerPC_MMA_ACC_PP_Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty]>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index 4da2969857d55..b7100462cb967 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -105,12 +105,15 @@ let Predicates = [IsISAFuture] in {
"dmxxinstfdmr256 $AT, $XBp, $P", []>;
def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
- "dmmr $AT, $AB", []>;
+ "dmmr $AT, $AB",
+ [(set v1024i1:$AT, (int_ppc_mma_dmmr v1024i1:$AB))]>;
def DMXOR : XForm_ATB3<31, 7, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB),
- "dmxor $AT, $AB", []>,
+ "dmxor $AT, $AB",
+ [(set v1024i1:$AT, (int_ppc_mma_dmxor v1024i1:$ATi, v1024i1:$AB))]>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
- "dmsetdmrz $AT", NoItinerary, []>;
+ "dmsetdmrz $AT", NoItinerary,
+ [(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
}
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| ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1 | ||
| ; CHECK-BE-NEXT: lxvp vsp34, 32(r3) | ||
| ; CHECK-BE-NEXT: lxvp vsp36, 0(r3) | ||
| ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0 |
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Maybe I am looking at an older RFC.. the version I am looking at contains dmxxinstdmr512 not dmxxinstfdmr512.
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I think dmxxinstfdmr512 was renamed to dmxxinstdmr512.
| ; CHECK-BE-NEXT: lxvp vsp36, 0(r4) | ||
| ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0 | ||
| ; CHECK-BE-NEXT: dmxor dmr0, dmr1 | ||
| ; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1 |
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For dmxxextfdmr512, shouldn't the signature be something like dmxxextfdmr512 vsp, vsp, wacc, 0|1?
dmxxextfdmr512 XAp,XBp,AS,
Register operand data layout:
* src : DMR[AS][4xP[+0..3]
* tgt : VSR[XAp[+1]] VSR[XBp[+1]]
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The older RFC that implemented/added this instruction had this signature dmxxextfdmr512 AS,XAp,XBp,P and the latest one has dmxxextfdmr512 XAp,XBp,AS,P.
It should be done in a separate patch. Yes, there would be updates required to other places. But also no this patch does not introduce an intrinsic for dmxxextfdmr512. That instruction just appears in a test case, where it was introduced indirectly by using a store. |
…structions (llvm#129913) Add intrinsics and tests for Dense Math basic enablement instructions dmsetdmrz, dmmr, dmxor.
Add intrinsics and tests for Dense Math basic enablement instructions dmsetdmrz, dmmr, dmxor.