Skip to content

[RISCV] Update to Xqciint v0.4 #130219

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Mar 11, 2025
Merged

[RISCV] Update to Xqciint v0.4 #130219

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
30cc006
[RISCV] Update to Xqciint v0.4
lenary Mar 7, 2025
4b39e6f
fixup! [RISCV] Update to Xqciint v0.4
lenary Mar 7, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion clang/include/clang/Basic/AttrDocs.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2848,7 +2848,7 @@ https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Function-Attributes.html
https://riscv.org/specifications/privileged-isa/
The RISC-V Instruction Set Manual Volume II: Privileged Architecture
Version 1.10.
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7
}];
}

Expand Down
2 changes: 1 addition & 1 deletion clang/test/Driver/print-supported-extensions-riscv.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -201,7 +201,7 @@
// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension)
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
// CHECK-NEXT: xqciint 0.4 'Xqciint' (Qualcomm uC Interrupts Extension)
// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
Expand Down
2 changes: 1 addition & 1 deletion llvm/docs/RISCVUsage.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -454,7 +454,7 @@ The current vendor extensions supported are:
LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.

``experimental-Xqciint``
LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
LLVM implements `version 0.4 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.

``experimental-Xqcilia``
LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVFeatures.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1351,7 +1351,7 @@ def HasVendorXqcicm
"'Xqcicm' (Qualcomm uC Conditional Move Extension)">;

def FeatureVendorXqciint
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Interrupts Extension",
: RISCVExperimentalExtension<0, 4, "Qualcomm uC Interrupts Extension",
[FeatureStdExtZca]>;
def HasVendorXqciint
: Predicate<"Subtarget->hasVendorXqciint()">,
Expand Down
7 changes: 3 additions & 4 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1008,10 +1008,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// The frame pointer does need to be reserved from register allocation.
assert(MF.getRegInfo().isReserved(FPReg) && "FP not reserved");

// Xqccmp with hasFP will update FP using `qc.cm.pushfp`, so we don't need
// to update it again, but we do need to emit the `.cfi_def_cfa` below.
if (RVFI->getPushPopKind(MF) !=
RISCVMachineFunctionInfo::PushPopKind::VendorXqccmp) {
// Some stack management variants automatically keep FP updated, so we don't
// need an instruction to do so.
if (!RVFI->hasImplicitFPUpdates(MF)) {
RI->adjustReg(
MBB, MBBI, DL, FPReg, SPReg,
StackOffset::getFixed(RealStackSize - RVFI->getVarArgsSaveSize()),
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -568,7 +568,7 @@ let Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1 in {

let mayLoad = 0, mayStore = 1,
Uses = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31],
Defs = [X2] in {
Defs = [X2, X8] in {
def QC_C_MIENTER : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
} // mayLoad = 1, mayStore = 1, Uses = [...], Defs = [...]
Expand Down
23 changes: 23 additions & 0 deletions llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,29 @@ RISCVMachineFunctionInfo::getPushPopKind(const MachineFunction &MF) const {
return PushPopKind::None;
}

bool RISCVMachineFunctionInfo::hasImplicitFPUpdates(
const MachineFunction &MF) const {
switch (getInterruptStackKind(MF)) {
case InterruptStackKind::QCINest:
case InterruptStackKind::QCINoNest:
// QC.C.MIENTER and QC.C.MIENTER.NEST both update FP on function entry.
return true;
default:
break;
}

switch (getPushPopKind(MF)) {
case PushPopKind::VendorXqccmp:
// When using Xqccmp, we will use `QC.CM.PUSHFP` when Frame Pointers are
// enabled, which will update FP.
return true;
default:
break;
}

return false;
}

void RISCVMachineFunctionInfo::initializeBaseYamlFields(
const yaml::RISCVMachineFunctionInfo &YamlMFI) {
VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -166,6 +166,12 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
unsigned getQCIInterruptStackSize() const { return QCIInterruptStackSize; }
void setQCIInterruptStackSize(unsigned Size) { QCIInterruptStackSize = Size; }

// Some Stack Management Variants automatically update FP in a frame-pointer
// convention compatible way - which means we don't need to manually update
// the FP, but we still need to emit the correct CFI information for
// calculating the CFA based on FP.
bool hasImplicitFPUpdates(const MachineFunction &MF) const;

void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI);

void addSExt32Register(Register Reg);
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/attributes.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -411,7 +411,7 @@
; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2"
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p2"
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p4"
; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
Expand Down
12 changes: 0 additions & 12 deletions llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,6 @@ define void @test_nest_empty() "interrupt"="qci-nest" {
; QCI-FP-NEXT: .cfi_offset t4, -72
; QCI-FP-NEXT: .cfi_offset t5, -76
; QCI-FP-NEXT: .cfi_offset t6, -80
; QCI-FP-NEXT: addi s0, sp, 96
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: .cfi_def_cfa sp, 96
; QCI-FP-NEXT: qc.c.mileaveret
Expand Down Expand Up @@ -140,7 +139,6 @@ define void @test_nonest_empty() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: .cfi_offset t4, -72
; QCI-FP-NEXT: .cfi_offset t5, -76
; QCI-FP-NEXT: .cfi_offset t6, -80
; QCI-FP-NEXT: addi s0, sp, 96
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: .cfi_def_cfa sp, 96
; QCI-FP-NEXT: qc.c.mileaveret
Expand Down Expand Up @@ -223,7 +221,6 @@ define void @test_nest_asm() "interrupt"="qci-nest" {
; QCI-FP-NEXT: .cfi_offset t4, -72
; QCI-FP-NEXT: .cfi_offset t5, -76
; QCI-FP-NEXT: .cfi_offset t6, -80
; QCI-FP-NEXT: addi s0, sp, 96
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: li a0, 1
; QCI-FP-NEXT: #APP
Expand Down Expand Up @@ -315,7 +312,6 @@ define void @test_nonest_asm() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: .cfi_offset t4, -72
; QCI-FP-NEXT: .cfi_offset t5, -76
; QCI-FP-NEXT: .cfi_offset t6, -80
; QCI-FP-NEXT: addi s0, sp, 96
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: li a0, 1
; QCI-FP-NEXT: #APP
Expand Down Expand Up @@ -423,7 +419,6 @@ define void @test_nest_call() "interrupt"="qci-nest" {
; QCI-FP-NEXT: .cfi_offset t6, -80
; QCI-FP-NEXT: addi sp, sp, -16
; QCI-FP-NEXT: .cfi_def_cfa_offset 112
; QCI-FP-NEXT: addi s0, sp, 112
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: li a0, 4
; QCI-FP-NEXT: li a2, 1
Expand Down Expand Up @@ -548,7 +543,6 @@ define void @test_nonest_call() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: .cfi_offset t6, -80
; QCI-FP-NEXT: addi sp, sp, -16
; QCI-FP-NEXT: .cfi_def_cfa_offset 112
; QCI-FP-NEXT: addi s0, sp, 112
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: li a0, 4
; QCI-FP-NEXT: li a2, 1
Expand Down Expand Up @@ -807,7 +801,6 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-FP-NEXT: .cfi_offset s9, -132
; QCI-FP-NEXT: .cfi_offset s10, -136
; QCI-FP-NEXT: .cfi_offset s11, -140
; QCI-FP-NEXT: addi s0, sp, 176
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: lui t1, %hi(var)
; QCI-FP-NEXT: lw a0, %lo(var)(t1)
Expand Down Expand Up @@ -1264,7 +1257,6 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: .cfi_offset s9, -132
; QCI-FP-NEXT: .cfi_offset s10, -136
; QCI-FP-NEXT: .cfi_offset s11, -140
; QCI-FP-NEXT: addi s0, sp, 176
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: lui t1, %hi(var)
; QCI-FP-NEXT: lw a0, %lo(var)(t1)
Expand Down Expand Up @@ -1765,7 +1757,6 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-FP-NEXT: .cfi_offset s9, -132
; QCI-FP-NEXT: .cfi_offset s10, -136
; QCI-FP-NEXT: .cfi_offset s11, -140
; QCI-FP-NEXT: addi s0, sp, 240
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: lui s6, %hi(var)
; QCI-FP-NEXT: lw a0, %lo(var)(s6)
Expand Down Expand Up @@ -2356,7 +2347,6 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: .cfi_offset s9, -132
; QCI-FP-NEXT: .cfi_offset s10, -136
; QCI-FP-NEXT: .cfi_offset s11, -140
; QCI-FP-NEXT: addi s0, sp, 240
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: lui s6, %hi(var)
; QCI-FP-NEXT: lw a0, %lo(var)(s6)
Expand Down Expand Up @@ -2768,7 +2758,6 @@ define void @test_nest_explicit_s11() "interrupt"="qci-nest" {
; QCI-FP-NEXT: .cfi_def_cfa_offset 112
; QCI-FP-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; QCI-FP-NEXT: .cfi_offset s11, -100
; QCI-FP-NEXT: addi s0, sp, 112
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: #APP
; QCI-FP-NEXT: li s4, 0
Expand Down Expand Up @@ -2877,7 +2866,6 @@ define void @test_nonest_explicit_s11() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: .cfi_def_cfa_offset 112
; QCI-FP-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; QCI-FP-NEXT: .cfi_offset s11, -100
; QCI-FP-NEXT: addi s0, sp, 112
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
; QCI-FP-NEXT: #APP
; QCI-FP-NEXT: li s11, 0
Expand Down
4 changes: 2 additions & 2 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -656,7 +656,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
for (StringRef Input :
{"rv64i_xqcisls0p2", "rv64i_xqcia0p4", "rv64i_xqciac0p3",
"rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2",
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2",
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p4",
"rv64i_xqcilo0p2", "rv64i_xqcilia0p2", "rv64i_xqcibm0p4"}) {
EXPECT_THAT(
toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
Expand Down Expand Up @@ -1132,7 +1132,7 @@ Experimental extensions
xqcicm 0.2
xqcics 0.2
xqcicsr 0.2
xqciint 0.2
xqciint 0.4
xqcilia 0.2
xqcilo 0.2
xqcilsm 0.2
Expand Down