[libunwind][RISCV] Make asm statement volatile

[futog]

Compiling with O3, the early-machinelicm pass hoisted the asm statement to a path that has been executed unconditionally during stack unwinding. On hardware without vector extension support, this resulted in reading a nonexistent register.

[llvmbot]

@llvm/pr-subscribers-libunwind

Author: Gergely Futo (futog)

Changes

Compiling with O3, the early-machinelicm pass hoisted the asm statement to a path that has been executed unconditionally during stack unwinding. On hardware without vector extension support, this resulted in reading a nonexistent register.

---

Full diff: https://github.com/llvm/llvm-project/pull/130286.diff

1 Files Affected:

• (modified) libunwind/src/Registers.hpp (+1-1)

diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp
index 452f46a0d56ea..3b28874c9ae32 100644
--- a/libunwind/src/Registers.hpp
+++ b/libunwind/src/Registers.hpp
@@ -4126,7 +4126,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const {
     return _registers[regNum];
   if (regNum == UNW_RISCV_VLENB) {
     reg_t vlenb;
-    __asm__("csrr %0, 0xC22" : "=r"(vlenb));
+    __asm__ volatile ("csrr %0, 0xC22" : "=r"(vlenb));
     return vlenb;
   }
   _LIBUNWIND_ABORT("unsupported riscv register");

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