Skip to content

[RISCV] Use vmv.v.x for any rv32 e64 splat with equal halves #130530

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Mar 10, 2025
Merged

[RISCV] Use vmv.v.x for any rv32 e64 splat with equal halves #130530

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
d95a0f9
[RISCV] Use vmv.v.x for any constant VL rv32 e64 splat with equal halves
preames Mar 9, 2025
1f06368
Switch to using vlmax form
preames Mar 10, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
28 changes: 10 additions & 18 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4361,27 +4361,19 @@ static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Passthru,
if ((LoC >> 31) == HiC)
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Lo, VL);

// If vl is equal to VLMAX or fits in 4 bits and Hi constant is equal to Lo,
// we could use vmv.v.x whose EEW = 32 to lower it. This allows us to use
// vlmax vsetvli or vsetivli to change the VL.
// FIXME: Support larger constants?
// FIXME: Support non-constant VLs by saturating?
// Use vmv.v.x with EEW=32. Use either a vsetivli or vsetvli to change
// VL. This can temporarily increase VL if VL less than VLMAX.
if (LoC == HiC) {
SDValue NewVL;
if (isAllOnesConstant(VL) ||
(isa<RegisterSDNode>(VL) &&
cast<RegisterSDNode>(VL)->getReg() == RISCV::X0))
NewVL = DAG.getRegister(RISCV::X0, MVT::i32);
else if (isa<ConstantSDNode>(VL) && isUInt<4>(VL->getAsZExtVal()))
if (isa<ConstantSDNode>(VL) && isUInt<4>(VL->getAsZExtVal()))
NewVL = DAG.getNode(ISD::ADD, DL, VL.getValueType(), VL, VL);

if (NewVL) {
MVT InterVT =
MVT::getVectorVT(MVT::i32, VT.getVectorElementCount() * 2);
auto InterVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterVT,
DAG.getUNDEF(InterVT), Lo, NewVL);
return DAG.getNode(ISD::BITCAST, DL, VT, InterVec);
}
else
NewVL = DAG.getRegister(RISCV::X0, MVT::i32);
MVT InterVT =
MVT::getVectorVT(MVT::i32, VT.getVectorElementCount() * 2);
auto InterVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterVT,
DAG.getUNDEF(InterVT), Lo, NewVL);
return DAG.getNode(ISD::BITCAST, DL, VT, InterVec);
}
}
Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Somewhat of an aside, if we wanted to avoid the vlse in general, we could use a vmv.v.x followed by a masked vmerge.vxm where the mask is 0101... to handle any hi/lo values. This isn't "better" per se, except that it avoids some memory traffic. For cores which don't implement the optimized broadcast load case, this might be a win. I don't have an example where this would be worthwhile, so I don't plan to pursue this now.


Expand Down
Loading
Loading