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[Mips] Fix clang crashes when compiling a variadic function while targeting mips3 #130558

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Merged
merged 1 commit into from
Apr 16, 2025
Merged

[Mips] Fix clang crashes when compiling a variadic function while targeting mips3 #130558

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10 changes: 7 additions & 3 deletions llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -37,9 +37,13 @@ ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
llvm_unreachable("Unhandled ABI");
}

ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
if (IsO32())
return ArrayRef(O32IntRegs);
ArrayRef<MCPhysReg> MipsABIInfo::getVarArgRegs(bool isGP64bit) const {
if (IsO32()) {
if (isGP64bit)
return ArrayRef(Mips64IntRegs);
else
return ArrayRef(O32IntRegs);
}
if (IsN32() || IsN64())
return ArrayRef(Mips64IntRegs);
llvm_unreachable("Unhandled ABI");
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
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Expand Up @@ -46,7 +46,7 @@ class MipsABIInfo {
ArrayRef<MCPhysReg> GetByValArgRegs() const;

/// The registers to use for the variable argument list.
ArrayRef<MCPhysReg> GetVarArgRegs() const;
ArrayRef<MCPhysReg> getVarArgRegs(bool isGP64bit) const;

/// Obtain the size of the area allocated by the callee for arguments.
/// CallingConv::FastCall affects the value for O32.
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3 changes: 2 additions & 1 deletion llvm/lib/Target/Mips/MipsCallLowering.cpp
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Expand Up @@ -406,7 +406,8 @@ bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
return false;

if (F.isVarArg()) {
ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
ArrayRef<MCPhysReg> ArgRegs =
ABI.getVarArgRegs(MF.getSubtarget<MipsSubtarget>().isGP64bit());
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);

int VaArgOffset;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsCallingConv.td
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Expand Up @@ -339,7 +339,7 @@ def CC_Mips_FixedArg : CallingConv<[

CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,

CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
CCIfSubtarget<"isABI_O32()", CCIfSubtargetNot<"isGP64bit()", CCDelegateTo<CC_MipsO32_FP>>>,
CCDelegateTo<CC_MipsN>
]>;

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3 changes: 1 addition & 2 deletions llvm/lib/Target/Mips/MipsISelLowering.cpp
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Expand Up @@ -3400,7 +3400,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDValue StackPtr =
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
getPointerTy(DAG.getDataLayout()));

std::deque<std::pair<unsigned, SDValue>> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;

Expand Down Expand Up @@ -4640,7 +4639,7 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
SDValue Chain, const SDLoc &DL,
SelectionDAG &DAG,
CCState &State) const {
ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
ArrayRef<MCPhysReg> ArgRegs = ABI.getVarArgRegs(Subtarget.isGP64bit());
unsigned Idx = State.getFirstUnallocated(ArgRegs);
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
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54 changes: 54 additions & 0 deletions llvm/test/CodeGen/Mips/vararg.ll
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@@ -0,0 +1,54 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips3 -target-abi o32 < %s | FileCheck %s -check-prefixes=MIPS3-O32
; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips3 -target-abi n32 < %s | FileCheck %s -check-prefixes=MIPS3-N32
; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips3 -target-abi n64 < %s | FileCheck %s -check-prefixes=MIPS3-N64

define void @func(ptr nocapture %x, ...) nounwind {
; MIPS3-O32-LABEL: func:
; MIPS32-O32: # %bb.0: # %entry
; MIPS32-O32-NEXT: addiu $sp, $sp, -48
; MIPS32-O32-NEXT: sd $11, 56($sp)
; MIPS32-O32-NEXT: sd $10, 48($sp)
; MIPS32-O32-NEXT: sd $9, 40($sp)
; MIPS32-O32-NEXT: sd $8, 32($sp)
; MIPS32-O32-NEXT: sd $7, 24($sp)
; MIPS32-O32-NEXT: sd $6, 16($sp)
; MIPS32-O32-NEXT: sd $5, 8($sp)
; MIPS32-O32-NEXT: sw $4, 4($sp)
; MIPS32-O32-NEXT: jr $ra
; MIPS32-O32-NEXT: addiu $sp, $sp, 48
;
; MIPS3-N32-LABEL: func:
; MIPS32-N32: # %bb.0: # %entry
; MIPS32-N32-NEXT: addiu $sp, $sp, -64
; MIPS32-N32-NEXT: sd $11, 56($sp)
; MIPS32-N32-NEXT: sd $10, 48($sp)
; MIPS32-N32-NEXT: sd $9, 40($sp)
; MIPS32-N32-NEXT: sd $8, 32($sp)
; MIPS32-N32-NEXT: sd $7, 24($sp)
; MIPS32-N32-NEXT: sd $6, 16($sp)
; MIPS32-N32-NEXT: sd $5, 8($sp)
; MIPS32-N32-NEXT: sw $4, 4($sp)
; MIPS32-N32-NEXT: jr $ra
; MIPS32-N32-NEXT: addiu $sp, $sp, 64
;
; MIPS3-N64-LABEL: func:
; MIPS32-N64: # %bb.0: # %entry
; MIPS32-N64-NEXT: addiu $sp, $sp, -64
; MIPS32-N64-NEXT: sdl $4, 7($sp)
; MIPS32-N64-NEXT: sd $11, 56($sp)
; MIPS32-N64-NEXT: sd $10, 48($sp)
; MIPS32-N64-NEXT: sd $9, 40($sp)
; MIPS32-N64-NEXT: sd $8, 32($sp)
; MIPS32-N64-NEXT: sd $7, 24($sp)
; MIPS32-N64-NEXT: sd $6, 16($sp)
; MIPS32-N64-NEXT: sd $5, 8($sp)
; MIPS32-N64-NEXT: sw $4, 4($sp)
; MIPS32-N64-NEXT: jr $ra
; MIPS32-N64-NEXT: addiu $sp, $sp, 64

entry:
%x.addr = alloca ptr, align 4
store ptr %x, ptr %x.addr, align 4
ret void
}
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