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[RISCV] Convert vsub.vx to vadd.vi if possible #130669

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Merged
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Mar 10, 2025
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[RISCV] Convert vsub.vx to vadd.vi if possible #130669

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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3573,6 +3573,13 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
/*Decrement=*/true);
}

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
/*Decrement=*/false);
}

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
SDValue &SplatVal) {
return selectVSplatImmHelper(
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1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
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Expand Up @@ -137,6 +137,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
return selectVSplatUimm(N, Bits, Val);
}
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
bool selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal);
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal);
// Matches the splat of a value which can be extended or truncated, such that
// only the bottom 8 bits are preserved.
Expand Down
13 changes: 11 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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Expand Up @@ -877,9 +877,9 @@ foreach mti = AllMasks in
// 11.1. Vector Single-Width Integer Add and Subtract
defm : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
defm : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
// Handle VRSUB specially since it's the only integer binary op with reversed
// pattern operands
foreach vti = AllIntegerVectors in {
// Handle VRSUB specially since it's the only integer binary op with reversed
// pattern operands
// FIXME: The AddedComplexity here is covering up a missing matcher for
// widening vwsub.vx which can recognize a extended folded into the
// scalar of the splat.
Expand All @@ -896,6 +896,15 @@ foreach vti = AllIntegerVectors in {
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
simm5:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
}

let Predicates = GetVTypePredicates<vti>.Predicates in {
// Match VSUB with a small immediate to vadd.vi by negating the immediate.
def : Pat<(sub (vti.Vector vti.RegClass:$rs1),
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I'm a bit surprised that DAGCombiner doesn't canonicalize this, but I checked the code and it's only canonicalizing scalars.

(vti.Vector (SplatPat_simm5_plus1_nodec simm5_plus1:$rs2))),
(!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
(NegImm simm5_plus1:$rs2), vti.AVL, vti.Log2SEW, TA_MA)>;
}
}

// 11.2. Vector Widening Integer Add and Subtract
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15 changes: 13 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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Expand Up @@ -598,6 +598,8 @@ def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimmBits<5>", [], [],
def SplatPat_uimm6 : ComplexPattern<vAny, 1, "selectVSplatUimmBits<6>", [], [], 3>;
def SplatPat_simm5_plus1
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 3>;
def SplatPat_simm5_plus1_nodec
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NoDec", [], [], 3>;
def SplatPat_simm5_plus1_nonzero
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 3>;

Expand Down Expand Up @@ -1992,10 +1994,10 @@ multiclass VPatAVGADDVL_VV_VX_RM<SDNode vop, int vxrm, string suffix = ""> {
// 11.1. Vector Single-Width Integer Add and Subtract
defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">;
defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">;
// Handle VRSUB specially since it's the only integer binary op with reversed
// pattern operands
foreach vti = AllIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
// Handle VRSUB specially since it's the only integer binary op with
// reversed pattern operands
def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))),
(vti.Vector vti.RegClass:$rs1),
vti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),
Expand All @@ -2008,6 +2010,15 @@ foreach vti = AllIntegerVectors in {
(!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK")
vti.RegClass:$passthru, vti.RegClass:$rs1, simm5:$rs2,
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;

// Match VSUB with a small immediate to vadd.vi by negating the immediate.
def : Pat<(riscv_sub_vl (vti.Vector vti.RegClass:$rs1),
(vti.Vector (SplatPat_simm5_plus1_nodec simm5_plus1:$rs2)),
vti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),
(!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX#"_MASK")
vti.RegClass:$passthru, vti.RegClass:$rs1,
(NegImm simm5_plus1:$rs2), (vti.Mask VMV0:$vm),
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}

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16 changes: 6 additions & 10 deletions llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
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Expand Up @@ -2585,8 +2585,7 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
; CHECK-NEXT: li a0, 7
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vi v8, v8, -7, v0.t
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i9:
Expand All @@ -2595,8 +2594,7 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
; CHECK-ZVBB-NEXT: li a0, 7
; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-ZVBB-NEXT: vadd.vi v8, v8, -7, v0.t
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i9> %v
Expand Down Expand Up @@ -2744,13 +2742,12 @@ define <vscale x 1 x i9> @vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor(<vsc
; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wi v8, v9, 23
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: vminu.vx v8, v8, a1
; CHECK-NEXT: li a0, 7
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vminu.vx v8, v8, a0
; CHECK-NEXT: vadd.vi v8, v8, -7
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor:
Expand All @@ -2761,8 +2758,7 @@ define <vscale x 1 x i9> @vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor(<vsc
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
; CHECK-ZVBB-NEXT: vclz.v v8, v8
; CHECK-ZVBB-NEXT: li a0, 7
; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0
; CHECK-ZVBB-NEXT: vadd.vi v8, v8, -7
; CHECK-ZVBB-NEXT: ret
%va.not = call <vscale x 1 x i9> @llvm.vp.xor.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i9> splat (i9 -1), <vscale x 1 x i1> %m, i32 %evl)
%v = call <vscale x 1 x i9> @llvm.ctlz(<vscale x 1 x i9> %va.not, i1 false)
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