[SPIR-V] Add support for HLSL SV_GroupIndex #130670

cassiebeckley · 2025-03-10T21:11:41Z

This PR lowers the llvm.spv.flattened.thread.id.in.group intrinsic as a LocalInvocationIndex builtin variable.

cassiebeckley · 2025-03-10T21:11:58Z

github-actions · 2025-03-10T21:12:02Z

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llvmbot · 2025-03-10T21:12:34Z

@llvm/pr-subscribers-backend-spir-v

@llvm/pr-subscribers-llvm-ir

Author: Cassandra Beckley (cassiebeckley)

Changes

This PR lowers the llvm.spv.flattened.thread.id.in.group intrinsic as a LocalInvocationIndex builtin variable.

Full diff: https://github.com/llvm/llvm-project/pull/130670.diff

4 Files Affected:

(modified) llvm/docs/SPIRVUsage.rst (+4)
(modified) llvm/include/llvm/IR/IntrinsicsSPIRV.td (+1)
(modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+44)
(added) llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupIndex.ll (+32)

diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 6a27e0efaec7f..fc23e45681c07 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -399,6 +399,10 @@ SPIR-V backend, along with their descriptions and argument details.
      - 32-bit Integer
      - `[32-bit Integer]`
      - Retrieves the thread ID within a workgroup. Essential for identifying execution context in parallel compute operations.
+   * - `int_spv_flattened_thread_id_in_group`
+     - 32-bit Integer
+     - `[32-bit Integer]`
+     - Provides a flattened index for a given thread within a given group (SV_GroupIndex)
    * - `int_spv_create_handle`
      - Pointer
      - `[8-bit Integer]`
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 7012ef3534c68..8c6d27bb45e0c 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -61,6 +61,7 @@ let TargetPrefix = "spv" in {
   def int_spv_thread_id : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
   def int_spv_group_id : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
   def int_spv_thread_id_in_group : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
+  def int_spv_flattened_thread_id_in_group : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrWillReturn]>;
   def int_spv_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>;
   def int_spv_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>;
   def int_spv_cross : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index b188f36ca9a9e..94c6b1960a02b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -341,6 +341,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
   bool loadVec3BuiltinInputID(SPIRV::BuiltIn::BuiltIn BuiltInValue,
                               Register ResVReg, const SPIRVType *ResType,
                               MachineInstr &I) const;
+  bool loadBuiltinInputID(SPIRV::BuiltIn::BuiltIn BuiltInValue,
+                          Register ResVReg, const SPIRVType *ResType,
+                          MachineInstr &I) const;
   bool loadHandleBeforePosition(Register &HandleReg, const SPIRVType *ResType,
                                 GIntrinsic &HandleDef, MachineInstr &Pos) const;
 };
@@ -3059,6 +3062,15 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
     // builtin variable
     return loadVec3BuiltinInputID(SPIRV::BuiltIn::WorkgroupId, ResVReg, ResType,
                                   I);
+  case Intrinsic::spv_flattened_thread_id_in_group:
+    // The HLSL SV_GroupIndex semantic is lowered to
+    // llvm.spv.flattened.thread.id.in.group() intrinsic in LLVM IR for SPIR-V
+    // backend.
+    //
+    // In SPIR-V backend, llvm.spv.flattened.thread.id.in.group is translated to
+    // a `LocalInvocationIndex` builtin variable
+    return loadBuiltinInputID(SPIRV::BuiltIn::LocalInvocationIndex, ResVReg,
+                              ResType, I);
   case Intrinsic::spv_fdot:
     return selectFloatDot(ResVReg, ResType, I);
   case Intrinsic::spv_udot:
@@ -4005,6 +4017,38 @@ bool SPIRVInstructionSelector::loadVec3BuiltinInputID(
   return Result && MIB.constrainAllUses(TII, TRI, RBI);
 }
 
+// Generate the instructions to load 32-bit integer builtin input IDs/Indices.
+// Like LocalInvocationIndex
+bool SPIRVInstructionSelector::loadBuiltinInputID(
+    SPIRV::BuiltIn::BuiltIn BuiltInValue, Register ResVReg,
+    const SPIRVType *ResType, MachineInstr &I) const {
+  MachineIRBuilder MIRBuilder(I);
+  const SPIRVType *U32Type = GR.getOrCreateSPIRVIntegerType(32, MIRBuilder);
+  const SPIRVType *PtrType = GR.getOrCreateSPIRVPointerType(
+      U32Type, MIRBuilder, SPIRV::StorageClass::Input);
+
+  // Create new register for the input ID builtin variable.
+  Register NewRegister =
+      MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
+  MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 64));
+  GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
+
+  // Build global variable with the necessary decorations for the input ID
+  // builtin variable.
+  Register Variable = GR.buildGlobalVariable(
+      NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr,
+      SPIRV::StorageClass::Input, nullptr, true, true,
+      SPIRV::LinkageType::Import, MIRBuilder, false);
+
+  // Load uint value from the global variable.
+  auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
+                 .addDef(ResVReg)
+                 .addUse(GR.getSPIRVTypeID(U32Type))
+                 .addUse(Variable);
+
+  return MIB.constrainAllUses(TII, TRI, RBI);
+}
+
 SPIRVType *SPIRVInstructionSelector::widenTypeToVec4(const SPIRVType *Type,
                                                      MachineInstr &I) const {
   MachineIRBuilder MIRBuilder(I);
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupIndex.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupIndex.ll
new file mode 100644
index 0000000000000..f21780c7576ca
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupIndex.ll
@@ -0,0 +1,32 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
+
+; CHECK-DAG:        %[[#int:]] = OpTypeInt 32 0
+; CHECK-DAG:        %[[#ptr_Input_int:]] = OpTypePointer Input %[[#int]]
+; CHECK-DAG:        %[[#LocalInvocationIndex:]] = OpVariable %[[#ptr_Input_int]] Input
+
+; CHECK-DAG:        OpEntryPoint GLCompute {{.*}} %[[#LocalInvocationIndex]]
+; CHECK-DAG:        OpName %[[#LocalInvocationIndex]] "__spirv_BuiltInLocalInvocationIndex"
+; CHECK-DAG:        OpDecorate %[[#LocalInvocationIndex]] LinkageAttributes "__spirv_BuiltInLocalInvocationIndex" Import
+; CHECK-DAG:        OpDecorate %[[#LocalInvocationIndex]] BuiltIn LocalInvocationIndex
+
+target triple = "spirv-unknown-vulkan-library"
+
+declare void @local_index_user(i32)
+
+; Function Attrs: convergent noinline norecurse
+define void @main() #1 {
+entry:
+
+; CHECK:        %[[#load:]] = OpLoad %[[#int]] %[[#LocalInvocationIndex]]
+  %1 = call i32 @llvm.spv.flattened.thread.id.in.group()
+
+  call spir_func void @local_index_user(i32 %1)
+  ret void
+}
+
+; Function Attrs: nounwind willreturn memory(none)
+declare i32 @llvm.spv.flattened.thread.id.in.group() #3
+
+attributes #1 = { convergent noinline norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #3 = { nounwind willreturn memory(none) }

This PR lowers the llvm.spv.flattened.thread.id.in.group intrinsic as a `LocalInvocationIndex` builtin variable.

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupIndex.ll

Keenuts

nit on the test, otherwise LGTM, thanks for this!

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupIndex.ll

s-perron · 2025-03-19T14:35:57Z

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

+  Register Variable = GR.buildGlobalVariable(
+      NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr,
+      SPIRV::StorageClass::Input, nullptr, true, true,
+      SPIRV::LinkageType::Import, MIRBuilder, false);


Changing this to false will build a variable without any linkage attribute.

Suggested change

Register Variable = GR.buildGlobalVariable(

NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr,

SPIRV::StorageClass::Input, nullptr, true, true,

SPIRV::LinkageType::Import, MIRBuilder, false);

Register Variable = GR.buildGlobalVariable(

NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr,

SPIRV::StorageClass::Input, nullptr, true, false,

SPIRV::LinkageType::Import, MIRBuilder, false);

github-actions · 2025-03-19T15:05:04Z

@cassiebeckley Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

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Lower the `SV_GroupIndex` semantic as the `llvm.spv.flattened.thread.id.in.group` intrinsic. Depends on #130670. --------- Co-authored-by: Steven Perron <[email protected]>

llvmbot added backend:SPIR-V llvm:ir labels Mar 10, 2025

cassiebeckley mentioned this pull request Mar 14, 2025

[HLSL] Add support for SV_GroupIndex in SPIR-V #130672

Merged

[SPIR-V] Add support for HLSL SV_GroupIndex

76245d4

This PR lowers the llvm.spv.flattened.thread.id.in.group intrinsic as a `LocalInvocationIndex` builtin variable.

cassiebeckley force-pushed the spirv-group-index branch from 6ee1aab to 76245d4 Compare March 14, 2025 22:24

s-perron reviewed Mar 17, 2025

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PR feedback

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Keenuts self-requested a review March 18, 2025 11:49

Keenuts approved these changes Mar 18, 2025

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llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupIndex.ll Outdated Show resolved Hide resolved

Remove check for linkage attributes

e75c5ee

cassiebeckley requested a review from s-perron March 18, 2025 18:08

s-perron approved these changes Mar 19, 2025

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s-perron reviewed Mar 19, 2025

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s-perron merged commit 1f15252 into llvm:main Mar 19, 2025
11 of 13 checks passed

cassiebeckley deleted the spirv-group-index branch March 19, 2025 16:27

cassiebeckley mentioned this pull request Mar 21, 2025

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