[RISCV] FeatureVendorXwchc should imply FeatureStdExtZca.

[topperc]

If we don't do this the binary emission won't set the compressed flag in the ELF header and won't emit alignment NOPs for R_RISCV_ALIGN correctly to support the existence of 2 byte instructions in the stream.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

If we don't do this the binary emission won't set the compressed flag in the ELF header and won't emit alignment NOPs for R_RISCV_ALIGN correctly to support the existence of 2 byte instructions in the stream.

---

Full diff: https://github.com/llvm/llvm-project/pull/130817.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+2-1)
• (modified) llvm/test/CodeGen/RISCV/attributes.ll (+1-1)

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 544ad14266183..21119f624339c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1281,7 +1281,8 @@ def HasVendorXMIPSLSP
 
 def FeatureVendorXwchc
     : RISCVExtension<2, 2,
-                     "WCH/QingKe additional compressed opcodes">;
+                     "WCH/QingKe additional compressed opcodes",
+                     [FeatureStdExtZca]>;
 def HasVendorXwchc
     : Predicate<"Subtarget->hasVendorXwchc()">,
       AssemblerPredicate<(all_of FeatureVendorXwchc),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index eaf54f879df17..5d4d96a52a0fd 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -402,7 +402,7 @@
 ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
 ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
-; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2"
+; RV32XWCHC: .attribute 5, "rv32i2p1_zca1p0_xwchc2p2"
 ; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p1"
 ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p4"
 ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3"

[lenary]

I do wonder whether we should propose a Zcnop to the architects which just contains c.nop. I'm not sure whether it fundamentally helps since if you have any 16-bit instructions your implementation likely has Zca, but this is the only bit of Zca we're actually relying on with these dependencies.

[ArcaneNibble]

Indeed, cores which support these instructions all support Zca