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merged 2 commits into from
Mar 12, 2025
Merged

AMDGPU: Replace undef with poison in tests using insertvalue #130895

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ca45b6d
AMDGPU: Replace undef with poison in tests using insertvalue
arsenm Mar 12, 2025
5dc585c
AMDGPU/GlobalISel: Replace insertvalue undef with poison
arsenm Mar 12, 2025
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22 changes: 11 additions & 11 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
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Expand Up @@ -64,7 +64,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_use(i32 inreg %src0, i32 inreg
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i32 %src1, -1
%and = and i32 %src0, %not.src1
%insert.0 = insertvalue { i32, i32 } undef, i32 %and, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %and, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %not.src1, 1
ret { i32, i32 } %insert.1
}
Expand All @@ -90,7 +90,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_foldable_use(i32 inreg %src0, i
%not.src2 = xor i32 %src2, -1
%and0 = and i32 %src0, %not.src2
%and1 = and i32 %src1, %not.src2
%insert.0 = insertvalue { i32, i32 } undef, i32 %and0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %and0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %and1, 1
ret { i32, i32 } %insert.1
}
Expand Down Expand Up @@ -211,7 +211,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_foldable_use(i64 inreg %src0, i
%not.src2 = xor i64 %src2, -1
%and0 = and i64 %src0, %not.src2
%and1 = and i64 %src1, %not.src2
%insert.0 = insertvalue { i64, i64 } undef, i64 %and0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %and0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %and1, 1
ret { i64, i64 } %insert.1
}
Expand All @@ -238,7 +238,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_use(i64 inreg %src0, i64 inreg
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i64 %src1, -1
%and = and i64 %src0, %not.src1
%insert.0 = insertvalue { i64, i64 } undef, i64 %and, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %and, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %not.src1, 1
ret { i64, i64 } %insert.1
}
Expand Down Expand Up @@ -408,7 +408,7 @@ define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1
%and = and i16 %src0, %not.src1
%insert.0 = insertvalue { i16, i16 } undef, i16 %and, 0
%insert.0 = insertvalue { i16, i16 } poison, i16 %and, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
ret { i16, i16 } %insert.1
}
Expand All @@ -434,7 +434,7 @@ define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_foldable_use(i16 inreg %src0, i
%not.src2 = xor i16 %src2, -1
%and0 = and i16 %src0, %not.src2
%and1 = and i16 %src1, %not.src2
%insert.0 = insertvalue { i16, i16 } undef, i16 %and0, 0
%insert.0 = insertvalue { i16, i16 } poison, i16 %and0, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %and1, 1
ret { i16, i16 } %insert.1
}
Expand Down Expand Up @@ -601,7 +601,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_use(<2 x i16> inreg %src0, <2

%cast.0 = bitcast <2 x i16> %and to i32
%cast.1 = bitcast <2 x i16> %not.src1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1
}
Expand Down Expand Up @@ -646,7 +646,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_foldable_use(<2 x i16> inreg

%cast.0 = bitcast <2 x i16> %and0 to i32
%cast.1 = bitcast <2 x i16> %and1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1
}
Expand Down Expand Up @@ -857,7 +857,7 @@ define amdgpu_ps { i48, i48 } @s_andn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
%and = and <3 x i16> %src0, %not.src1
%cast.0 = bitcast <3 x i16> %and to i48
%cast.1 = bitcast <3 x i16> %not.src1 to i48
%insert.0 = insertvalue { i48, i48 } undef, i48 %cast.0, 0
%insert.0 = insertvalue { i48, i48 } poison, i48 %cast.0, 0
%insert.1 = insertvalue { i48, i48 } %insert.0, i48 %cast.1, 1
ret { i48, i48 } %insert.1
}
Expand Down Expand Up @@ -1028,7 +1028,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_use(<4 x i16> inreg %src0, <4

%cast.0 = bitcast <4 x i16> %and to i64
%cast.1 = bitcast <4 x i16> %not.src1 to i64
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
ret { i64, i64 } %insert.1
}
Expand Down Expand Up @@ -1082,7 +1082,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_foldable_use(<4 x i16> inreg

%cast.0 = bitcast <4 x i16> %and0 to i64
%cast.1 = bitcast <4 x i16> %and1 to i64
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
ret { i64, i64 } %insert.1
}
Expand Down
6 changes: 4 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
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Expand Up @@ -1061,6 +1061,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
Expand All @@ -1083,7 +1084,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
%insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
%insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2
%insert.3 = insertvalue { <3 x i32>, i32 } undef, <3 x i32> %insert.2, 0
%insert.3 = insertvalue { <3 x i32>, i32 } poison, <3 x i32> %insert.2, 0
%insert.4 = insertvalue { <3 x i32>, i32 } %insert.3, i32 %load3, 1
ret { <3 x i32>, i32 } %insert.4
}
Expand All @@ -1096,6 +1097,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
Expand All @@ -1118,7 +1120,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
%insert.0 = insertelement <3 x float> undef, float %load0, i32 0
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
%insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2
%insert.3 = insertvalue { <3 x float>, i32 } undef, <3 x float> %insert.2, 0
%insert.3 = insertvalue { <3 x float>, i32 } poison, <3 x float> %insert.2, 0
%insert.4 = insertvalue { <3 x float>, i32 } %insert.3, i32 %load3, 1
ret { <3 x float>, i32 } %insert.4
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
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Expand Up @@ -104,7 +104,7 @@ define amdgpu_ps { i32, i32 } @sgpr_struct_return_i32_i32(i32 %vgpr0, i32 %vgpr1
; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%insertvalue0 = insertvalue { i32, i32 } undef, i32 %vgpr0, 0
%insertvalue0 = insertvalue { i32, i32 } poison, i32 %vgpr0, 0
%value = insertvalue { i32, i32 } %insertvalue0, i32 %vgpr1, 1
ret { i32, i32 } %value
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
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Expand Up @@ -88,7 +88,7 @@ define amdgpu_vs <{ i32, i32 }> @ret_struct(i32 inreg %arg0, i32 inreg %arg1) {
; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
main_body:
%tmp0 = insertvalue <{ i32, i32 }> undef, i32 %arg0, 0
%tmp0 = insertvalue <{ i32, i32 }> poison, i32 %arg0, 0
%tmp1 = insertvalue <{ i32, i32 }> %tmp0, i32 %arg1, 1
ret <{ i32, i32 }> %tmp1
}
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
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Expand Up @@ -64,7 +64,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_use(i32 inreg %src0, i32 inreg %
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i32 %src1, -1
%or = or i32 %src0, %not.src1
%insert.0 = insertvalue { i32, i32 } undef, i32 %or, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %or, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %not.src1, 1
ret { i32, i32 } %insert.1
}
Expand All @@ -90,7 +90,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_foldable_use(i32 inreg %src0, i3
%not.src2 = xor i32 %src2, -1
%or0 = or i32 %src0, %not.src2
%or1 = or i32 %src1, %not.src2
%insert.0 = insertvalue { i32, i32 } undef, i32 %or0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %or0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %or1, 1
ret { i32, i32 } %insert.1
}
Expand Down Expand Up @@ -211,7 +211,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_foldable_use(i64 inreg %src0, i6
%not.src2 = xor i64 %src2, -1
%or0 = or i64 %src0, %not.src2
%or1 = or i64 %src1, %not.src2
%insert.0 = insertvalue { i64, i64 } undef, i64 %or0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %or0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %or1, 1
ret { i64, i64 } %insert.1
}
Expand All @@ -238,7 +238,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_use(i64 inreg %src0, i64 inreg %
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i64 %src1, -1
%or = or i64 %src0, %not.src1
%insert.0 = insertvalue { i64, i64 } undef, i64 %or, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %or, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %not.src1, 1
ret { i64, i64 } %insert.1
}
Expand Down Expand Up @@ -408,7 +408,7 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg %
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1
%or = or i16 %src0, %not.src1
%insert.0 = insertvalue { i16, i16 } undef, i16 %or, 0
%insert.0 = insertvalue { i16, i16 } poison, i16 %or, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
ret { i16, i16 } %insert.1
}
Expand All @@ -434,7 +434,7 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_foldable_use(i16 inreg %src0, i1
%not.src2 = xor i16 %src2, -1
%or0 = or i16 %src0, %not.src2
%or1 = or i16 %src1, %not.src2
%insert.0 = insertvalue { i16, i16 } undef, i16 %or0, 0
%insert.0 = insertvalue { i16, i16 } poison, i16 %or0, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %or1, 1
ret { i16, i16 } %insert.1
}
Expand Down Expand Up @@ -601,7 +601,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_use(<2 x i16> inreg %src0, <2

%cast.0 = bitcast <2 x i16> %or to i32
%cast.1 = bitcast <2 x i16> %not.src1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1
}
Expand Down Expand Up @@ -646,7 +646,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_foldable_use(<2 x i16> inreg %

%cast.0 = bitcast <2 x i16> %or0 to i32
%cast.1 = bitcast <2 x i16> %or1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1
}
Expand Down Expand Up @@ -856,7 +856,7 @@ define amdgpu_ps { i48, i48 } @s_orn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
%or = or <3 x i16> %src0, %not.src1
%cast.0 = bitcast <3 x i16> %or to i48
%cast.1 = bitcast <3 x i16> %not.src1 to i48
%insert.0 = insertvalue { i48, i48 } undef, i48 %cast.0, 0
%insert.0 = insertvalue { i48, i48 } poison, i48 %cast.0, 0
%insert.1 = insertvalue { i48, i48 } %insert.0, i48 %cast.1, 1
ret { i48, i48 } %insert.1
}
Expand Down Expand Up @@ -1027,7 +1027,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_use(<4 x i16> inreg %src0, <4

%cast.0 = bitcast <4 x i16> %or to i64
%cast.1 = bitcast <4 x i16> %not.src1 to i64
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
ret { i64, i64 } %insert.1
}
Expand Down Expand Up @@ -1081,7 +1081,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_foldable_use(<4 x i16> inreg %

%cast.0 = bitcast <4 x i16> %or0 to i64
%cast.1 = bitcast <4 x i16> %or1 to i64
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
ret { i64, i64 } %insert.1
}
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll
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Expand Up @@ -476,7 +476,7 @@ define amdgpu_ps { i32, i32 } @s_shl4_add_u32_multi_use(i32 inreg %src0, i32 inr
; GCN-NEXT: ; return to shader part epilog
%shl = shl i32 %src0, 4
%add = add i32 %shl, %src1
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
ret { i32, i32 } %insert1
}
Expand All @@ -489,7 +489,7 @@ define amdgpu_ps { i32, i32 } @s_shl3_add_u32_multi_use(i32 inreg %src0, i32 inr
; GCN-NEXT: ; return to shader part epilog
%shl = shl i32 %src0, 3
%add = add i32 %shl, %src1
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
ret { i32, i32 } %insert1
}
Expand All @@ -502,7 +502,7 @@ define amdgpu_ps { i32, i32 } @s_shl2_add_u32_multi_use(i32 inreg %src0, i32 inr
; GCN-NEXT: ; return to shader part epilog
%shl = shl i32 %src0, 2
%add = add i32 %shl, %src1
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
ret { i32, i32 } %insert1
}
Expand All @@ -516,7 +516,7 @@ define amdgpu_ps { i32, i32 } @s_shl1_add_u32_multi_use(i32 inreg %src0, i32 inr
; GCN-NEXT: ; return to shader part epilog
%shl = shl i32 %src0, 1
%add = add i32 %shl, %src1
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
ret { i32, i32 } %insert1
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
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Expand Up @@ -62,7 +62,7 @@ define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i
%56 = add i32 %55, %27
%57 = add i32 %56, %28
%58 = add i32 %57, %29
%59 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } undef, i32 %30, 0
%59 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } poison, i32 %30, 0
%60 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %59, i32 %31, 1
%61 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %60, i32 %32, 2
%62 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %61, i32 %33, 3
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
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Expand Up @@ -50,7 +50,7 @@ define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i
%88 = add i32 %87, %43
%89 = add i32 %88, %44
%90 = add i32 %89, %45
%91 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } undef, i32 %46, 0
%91 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } poison, i32 %46, 0
%92 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %91, i32 %47, 1
%93 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %92, i32 %48, 2
%94 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %93, i32 %49, 3
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
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Expand Up @@ -247,7 +247,7 @@ main_body:
%34 = extractelement <4 x float> %31, i32 2
%35 = extractelement <4 x float> %31, i32 3
%36 = bitcast float %4 to i32
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %36, 4
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison, i32 %36, 4
%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %32, 5
%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 6
%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 7
Expand Down Expand Up @@ -279,7 +279,7 @@ main_body:
%34 = extractelement <4 x float> %31, i32 2
%35 = extractelement <4 x float> %31, i32 3
%36 = bitcast float %4 to i32
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %36, 4
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison, i32 %36, 4
%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %32, 5
%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 6
%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 7
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
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Expand Up @@ -168,7 +168,7 @@ bb1:
%val1 = extractvalue { <4 x i32>, <4 x half> } %split.ret.type, 1
%extract0 = extractelement <4 x i32> %val0, i32 0
%extract1 = extractelement <4 x half> %val1, i32 0
%ins0 = insertvalue { i32, half } undef, i32 %extract0, 0
%ins0 = insertvalue { i32, half } poison, i32 %extract0, 0
%ins1 = insertvalue { i32, half } %ins0, half %extract1, 1
ret { i32, half } %ins1
}
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
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Expand Up @@ -30,7 +30,7 @@ bb:
%tmp3 = fsub fast double %arg2, %arg
%tmp4 = fadd fast double %tmp3, %tmp
%tmp5 = fsub fast double %tmp, %tmp3
%tmp6 = insertvalue { double, double } undef, double %tmp4, 0
%tmp6 = insertvalue { double, double } poison, double %tmp4, 0
%tmp7 = insertvalue { double, double } %tmp6, double %tmp5, 1
ret { double, double } %tmp7
}
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