[X86][GISel] Use Register and MCRegister. NFC

[topperc]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-x86

Author: Craig Topper (topperc)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/130907.diff

2 Files Affected:

• (modified) llvm/lib/Target/X86/GISel/X86CallLowering.cpp (+4-4)
• (modified) llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp (+12-12)

diff --git a/llvm/lib/Target/X86/GISel/X86CallLowering.cpp b/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
index e84ee879a8323..c0a6035b792dc 100644
--- a/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
+++ b/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
@@ -218,14 +218,14 @@ struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
                         const CCValAssign &VA) override {
-    markPhysRegUsed(PhysReg);
+    markPhysRegUsed(PhysReg.asMCReg());
     IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
   }
 
   /// How the physical register gets marked varies between formal
   /// parameters (it's a basic-block live-in), and a call instruction
   /// (it's an implicit-def of the BL).
-  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
+  virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
 
 protected:
   const DataLayout &DL;
@@ -235,7 +235,7 @@ struct FormalArgHandler : public X86IncomingValueHandler {
   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
       : X86IncomingValueHandler(MIRBuilder, MRI) {}
 
-  void markPhysRegUsed(unsigned PhysReg) override {
+  void markPhysRegUsed(MCRegister PhysReg) override {
     MIRBuilder.getMRI()->addLiveIn(PhysReg);
     MIRBuilder.getMBB().addLiveIn(PhysReg);
   }
@@ -246,7 +246,7 @@ struct CallReturnHandler : public X86IncomingValueHandler {
                     MachineInstrBuilder &MIB)
       : X86IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
 
-  void markPhysRegUsed(unsigned PhysReg) override {
+  void markPhysRegUsed(MCRegister PhysReg) override {
     MIB.addDef(PhysReg, RegState::Implicit);
   }
 
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index d7f315d82b832..64a1fa1780a77 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -107,9 +107,9 @@ class X86InstructionSelector : public InstructionSelector {
   bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
                         MachineFunction &MF) const;
   bool selectTurnIntoCOPY(MachineInstr &I, MachineRegisterInfo &MRI,
-                          const unsigned DstReg,
+                          const Register DstReg,
                           const TargetRegisterClass *DstRC,
-                          const unsigned SrcReg,
+                          const Register SrcReg,
                           const TargetRegisterClass *SrcRC) const;
   bool materializeFP(MachineInstr &I, MachineRegisterInfo &MRI,
                      MachineFunction &MF) const;
@@ -120,14 +120,14 @@ class X86InstructionSelector : public InstructionSelector {
                     MachineFunction &MF) const;
 
   // emit insert subreg instruction and insert it before MachineInstr &I
-  bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
+  bool emitInsertSubreg(Register DstReg, Register SrcReg, MachineInstr &I,
                         MachineRegisterInfo &MRI, MachineFunction &MF) const;
   // emit extract subreg instruction and insert it before MachineInstr &I
-  bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
+  bool emitExtractSubreg(Register DstReg, Register SrcReg, MachineInstr &I,
                          MachineRegisterInfo &MRI, MachineFunction &MF) const;
 
   const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
-  const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
+  const TargetRegisterClass *getRegClass(LLT Ty, Register Reg,
                                          MachineRegisterInfo &MRI) const;
 
   const X86TargetMachine &TM;
@@ -207,7 +207,7 @@ X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
 }
 
 const TargetRegisterClass *
-X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
+X86InstructionSelector::getRegClass(LLT Ty, Register Reg,
                                     MachineRegisterInfo &MRI) const {
   const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
   return getRegClass(Ty, RegBank);
@@ -602,7 +602,7 @@ bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I,
       return false;
 
     unsigned char OpFlag = STI.classifyLocalReference(nullptr);
-    unsigned PICBase = 0;
+    Register PICBase;
     if (OpFlag == X86II::MO_GOTOFF)
       PICBase = TII.getGlobalBaseReg(&MF);
     else if (STI.is64Bit())
@@ -771,8 +771,8 @@ static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC,
 }
 
 bool X86InstructionSelector::selectTurnIntoCOPY(
-    MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
-    const TargetRegisterClass *DstRC, const unsigned SrcReg,
+    MachineInstr &I, MachineRegisterInfo &MRI, const Register DstReg,
+    const TargetRegisterClass *DstRC, const Register SrcReg,
     const TargetRegisterClass *SrcRC) const {
 
   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
@@ -1288,7 +1288,7 @@ bool X86InstructionSelector::selectExtract(MachineInstr &I,
   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 }
 
-bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg,
+bool X86InstructionSelector::emitExtractSubreg(Register DstReg, Register SrcReg,
                                                MachineInstr &I,
                                                MachineRegisterInfo &MRI,
                                                MachineFunction &MF) const {
@@ -1326,7 +1326,7 @@ bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg,
   return true;
 }
 
-bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg,
+bool X86InstructionSelector::emitInsertSubreg(Register DstReg, Register SrcReg,
                                               MachineInstr &I,
                                               MachineRegisterInfo &MRI,
                                               MachineFunction &MF) const {
@@ -1841,7 +1841,7 @@ bool X86InstructionSelector::selectSelect(MachineInstr &I,
                                           MachineRegisterInfo &MRI,
                                           MachineFunction &MF) const {
   GSelect &Sel = cast<GSelect>(I);
-  unsigned DstReg = Sel.getReg(0);
+  Register DstReg = Sel.getReg(0);
   BuildMI(*Sel.getParent(), Sel, Sel.getDebugLoc(), TII.get(X86::TEST32rr))
       .addReg(Sel.getCondReg())
       .addReg(Sel.getCondReg());

[topperc]

I'm using asMCReg() here to assert that PhysReg is really a physical register instead of silently implicitly converting to MCRegister. addLiveIn used by one of the overrides of markPhysRegUsed uses MCRegister so I converted early.

[e-kud]

Just finished checking, no unexpected failures on benchmarks.

[RKSimon]

LGTM