[CodeGenPrepare][RISCV] Combine (X ^ Y) and (X == Y) where appropriate #130922

bababuck · 2025-03-12T07:46:57Z

In RISCV, modify the folding of (X ^ Y == 0) -> (X == Y) to account for cases where the (X ^ Y) will be re-used.

If a constant is being used for the XOR before a branch, ensure that it is small enough to fit within a 12-bit immediate field. Otherwise, the equality check is more efficient than the check against 0, see the following:

# %bb.0:
        lui     a1, 5
        addiw   a1, a1, 1365
        xor     a0, a0, a1
        beqz    a0, .LBB0_2
# %bb.1: 
        ret
.LBB0_2:

# %bb.0:
        lui     a1, 5
        addiw   a1, a1, 1365
        beq    a0, a1, .LBB0_2
# %bb.1: 
        xor     a0, a0, a1
        ret
.LBB0_2:

Similarly, if the XOR is between 1 and a size one integer, we should still fold away the XOR since that comparison can be optimized as a comparison against 0.

# %bb.0:
        slt a0, a0, a1
        xor  a0, a0, 1
        beqz    a0, .LBB0_2
# %bb.1: 
        ret
.LBB0_2:

# %bb.0:
        slt a0, a0, a1
        bnez    a0, .LBB0_2
# %bb.1: 
        xor  a0, a0, 1
        ret
.LBB0_2:

One question about my code is that I used a hard-coded value for the width of a RISCV ALU immediate. Do you know of a way that I can gather this from the context, I was unable to devise one.

github-actions · 2025-03-12T07:47:16Z

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llvmbot · 2025-03-12T07:47:49Z

@llvm/pr-subscribers-backend-risc-v

Author: Ryan Buchner (bababuck)

Changes

Fixes #130510.

In RISCV, modify the folding of (X ^ Y == 0) -> (X == Y) to account for cases where the (X ^ Y) will be re-used.

If a constant is being used for the XOR before a branch, ensure that it is small enough to fit within a 12-bit immediate field. Otherwise, the equality check is more efficient than the check against 0, see the following:

# %bb.0:
        lui     a1, 5
        addiw   a1, a1, 1365
        xor     a0, a0, a1
        beqz    a0, .LBB0_2
# %bb.1: 
        ret
.LBB0_2:

# %bb.0:
        lui     a1, 5
        addiw   a1, a1, 1365
        beq    a0, a1, .LBB0_2
# %bb.1: 
        xor     a0, a0, a1
        ret
.LBB0_2:

Similarly, if the XOR is between 1 and a size one integer, we should still fold away the XOR since that comparison can be optimized as a comparison against 0.

# %bb.0:
        slt a0, a0, a1
        xor  a0, a0, 1
        beqz    a0, .LBB0_2
# %bb.1: 
        ret
.LBB0_2:

# %bb.0:
        slt a0, a0, a1
        bnez    a0, .LBB0_2
# %bb.1: 
        xor  a0, a0, 1
        ret
.LBB0_2:

One question about my code is that I used a hard-coded value for the width of a RISCV ALU immediate. Do you know of a way that I can gather this from the context, I was unable to devise one.

Full diff: https://github.com/llvm/llvm-project/pull/130922.diff

3 Files Affected:

(modified) llvm/lib/CodeGen/CodeGenPrepare.cpp (+2-1)
(modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+40-1)
(modified) llvm/test/CodeGen/RISCV/select-constant-xor.ll (+40)

diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index d5fbd4c380746..2acb7cb321d07 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -8578,7 +8578,8 @@ static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI,
     }
     if (Cmp->isEquality() &&
         (match(UI, m_Add(m_Specific(X), m_SpecificInt(-CmpC))) ||
-         match(UI, m_Sub(m_Specific(X), m_SpecificInt(CmpC))))) {
+         match(UI, m_Sub(m_Specific(X), m_SpecificInt(CmpC))) ||
+         match(UI, m_Xor(m_Specific(X), m_SpecificInt(CmpC))))) {
       IRBuilder<> Builder(Branch);
       if (UI->getParent() != Branch->getParent())
         UI->moveBefore(Branch->getIterator());
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 27a4bbce1f5fc..3abc835376f7b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17194,8 +17194,47 @@ static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
     return true;
   }
 
+  // If XOR is reused and has an immediate that will fit in XORI,
+  // do not fold
+  auto Is12BitConstant = [](const SDValue &Op) -> bool {
+    if (Op.getOpcode() == ISD::Constant) {
+      const int64_t RiscvAluImmBits = 12;
+      const int64_t RiscvAluImmUpperBound = (1 << RiscvAluImmBits) - 1;
+      const int64_t RiscvAluImmLowerBound = -(1 << RiscvAluImmBits);
+      const int64_t XorCnst =
+          llvm::dyn_cast<llvm::ConstantSDNode>(Op)->getSExtValue();
+      return (XorCnst >= RiscvAluImmLowerBound) &&
+             (XorCnst <= RiscvAluImmUpperBound);
+    }
+    return false;
+  };
+  // Fold (X(i1) ^ 1) == 0 -> X != 0
+  auto SingleBitOp = [&DAG](const SDValue &VarOp,
+                            const SDValue &ConstOp) -> bool {
+    if (ConstOp.getOpcode() == ISD::Constant) {
+      const int64_t XorCnst =
+          llvm::dyn_cast<llvm::ConstantSDNode>(ConstOp)->getSExtValue();
+      const APInt Mask = APInt::getBitsSetFrom(VarOp.getValueSizeInBits(), 1);
+      return (XorCnst == 1) && DAG.MaskedValueIsZero(VarOp, Mask);
+    }
+    return false;
+  };
+  auto OnlyUsedBySelectOrBR = [](const SDValue &Op) -> bool {
+    for (const SDUse &Use : Op->uses()) {
+      const SDNode *UseNode = Use.getUser();
+      const unsigned Opcode = UseNode->getOpcode();
+      if (Opcode != RISCVISD::SELECT_CC && Opcode != RISCVISD::BR_CC) {
+        return false;
+      }
+    }
+    return true;
+  };
+
   // Fold ((xor X, Y), 0, eq/ne) -> (X, Y, eq/ne)
-  if (LHS.getOpcode() == ISD::XOR && isNullConstant(RHS)) {
+  if (LHS.getOpcode() == ISD::XOR && isNullConstant(RHS) &&
+      (!Is12BitConstant(LHS.getOperand(1)) ||
+       SingleBitOp(LHS.getOperand(0), LHS.getOperand(1))) &&
+      OnlyUsedBySelectOrBR(LHS)) {
     RHS = LHS.getOperand(1);
     LHS = LHS.getOperand(0);
     return true;
diff --git a/llvm/test/CodeGen/RISCV/select-constant-xor.ll b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
index 2e26ae78e2dd8..f24e03ecd7d67 100644
--- a/llvm/test/CodeGen/RISCV/select-constant-xor.ll
+++ b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
@@ -239,3 +239,43 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
   %x = add i32 %s, %s2
   ret i32 %x
 }
+
+define i32 @xor_branch_ret(i32 %x) {
+; RV32-LABEL: xor_branch_ret:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    xori a0, a0, -1365
+; RV32-NEXT:    beqz a0, .LBB11_2
+; RV32-NEXT:  # %bb.1: # %if.then
+; RV32-NEXT:    ret
+; RV32-NEXT:  .LBB11_2: # %if.end
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    call abort
+;
+; RV64-LABEL: xor_branch_ret:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    xori a0, a0, -1365
+; RV64-NEXT:    sext.w a1, a0
+; RV64-NEXT:    beqz a1, .LBB11_2
+; RV64-NEXT:  # %bb.1: # %if.then
+; RV64-NEXT:    ret
+; RV64-NEXT:  .LBB11_2: # %if.end
+; RV64-NEXT:    addi sp, sp, -16
+; RV64-NEXT:    .cfi_def_cfa_offset 16
+; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    call abort
+entry:
+  %cmp.not = icmp eq i32 %x, -1365
+  br i1 %cmp.not, label %if.end, label %if.then
+if.then:
+  %xor = xor i32 %x, -1365
+  ret i32 %xor
+if.end:
+    tail call void @abort() #2
+  unreachable
+}
+
+declare void @abort()

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

llvm/test/CodeGen/RISCV/select-constant-xor.ll

llvm/lib/CodeGen/CodeGenPrepare.cpp

topperc · 2025-03-12T16:56:33Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+    return false;
+  };
+  auto OnlyUsedBySelectOrBR = [](const SDValue &Op) -> bool {
+    for (const SDUse &Use : Op->uses()) {


You can use Op->users()

topperc · 2025-03-12T16:57:39Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+                            const SDValue &ConstOp) -> bool {
+    if (ConstOp.getOpcode() == ISD::Constant) {
+      const int64_t XorCnst =
+          llvm::dyn_cast<llvm::ConstantSDNode>(ConstOp)->getSExtValue();


The llvm:: is unnecessary. Move the dyn_cast into the if instead of checking the opcode.

topperc · 2025-03-12T16:57:49Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+      const int64_t RiscvAluImmBits = 12;
+      const int64_t RiscvAluImmUpperBound = (1 << RiscvAluImmBits) - 1;
+      const int64_t RiscvAluImmLowerBound = -(1 << RiscvAluImmBits);
+      const int64_t XorCnst =


The llvm:: is unnecessary. Move the dyn_cast into the if instead of checking the opcode.

topperc · 2025-03-12T16:58:51Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+  auto Is12BitConstant = [](const SDValue &Op) -> bool {
+    if (Op.getOpcode() == ISD::Constant) {
+      const int64_t RiscvAluImmBits = 12;
+      const int64_t RiscvAluImmUpperBound = (1 << RiscvAluImmBits) - 1;


Use isInt<12> like the rest of the RISCV backend.

bababuck · 2025-03-12T21:37:36Z

I addressed the above comments, but I came across one issue in my tests:

When working with riscv64 with i32 an i32 input (a0 is i32), the following code generation occurs:

entry:
  %cmp.not = icmp eq i32 %x, 2048
  br i1 %cmp.not, label %if.end, label %if.then
if.then:
  %xor = xor i32 %x, 2048
  ret i32 %xor
if.end:
    tail call void @abort() #2
  unreachable

----->

# %bb.0:
   li a1, 1
   slli a1, a1, 11
   xor a0, a0, a1
   sext.w a1, a0
   beqz a1, .LBB0_2
# %bb.1: 
        ret
.LBB0_2:

Because the result of the sign extension is being used for the comparison, it does not matching the XOR folding pattern.

One though is that this sign extension is not needed because we are comparing against 0, so we can fold away the sign-extension. However, I'm not sure if that is legal or not (i.e. is an LLVM i32 guaranteed to have the upper bits 0'ed when compiling to a 64 bit architecture).

Any thoughts on how to proceed? I want to make sure I am not completely off track.

topperc · 2025-03-12T21:46:17Z

I addressed the above comments, but I came across one issue in my tests:

When working with riscv64 with i32 an i32 input (a0 is i32), the following code generation occurs:
entry:
  %cmp.not = icmp eq i32 %x, 2048
  br i1 %cmp.not, label %if.end, label %if.then
if.then:
  %xor = xor i32 %x, 2048
  ret i32 %xor
if.end:
    tail call void @abort() #2
  unreachable

----->

# %bb.0:
   li a1, 1
   slli a1, a1, 11
   xor a0, a0, a1
   sext.w a1, a0
   beqz a1, .LBB0_2
# %bb.1: 
        ret
.LBB0_2: 
Because the result of the sign extension is being used for the comparison, it does not matching the XOR folding pattern.

One though is that this sign extension is not needed because we are comparing against 0, so we can fold away the sign-extension. However, I'm not sure if that is legal or not (i.e. is an LLVM i32 guaranteed to have the upper bits 0'ed when compiling to a 64 bit architecture).

If %x is a function argument with the signext attribute we can assume the i32 is sign extended to the full register size. Likewise the zeroext attribute allows us to assume it is zero extended. If neither attribute is present, we can't make any assumptions. The clang frontend should always put signext on i32 function arguments to match the psABI.

topperc · 2025-03-12T21:48:57Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+  // do not fold
+  auto IsXorImmediate = [](const SDValue &Op) -> bool {
+    if (const auto XorCnst = dyn_cast<ConstantSDNode>(Op)) {
+      auto isLegalXorImmediate = [](int64_t Imm) -> bool {


This lambda doesn't really improve the code. Just use the isInt<12> directly.

topperc · 2025-03-12T21:49:58Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+  auto OnlyUsedBySelectOrBR = [](const SDValue &Op) -> bool {
+    for (const SDNode *UserNode : Op->users()) {
+      const unsigned Opcode = UserNode->getOpcode();
+      if (Opcode != RISCVISD::SELECT_CC && Opcode != RISCVISD::BR_CC) {


Drop curly braces

topperc · 2025-03-12T21:50:43Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -17194,8 +17194,41 @@ static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
    return true;
  }

+  // If XOR is reused and has an immediate that will fit in XORI,
+  // do not fold


Add a period to make this a complete sentence.

bababuck · 2025-03-12T21:56:59Z

If %x is a function argument with the signext attribute we can assume the i32 is sign extended to the full register size. Likewise the zeroext attribute allows us to assume it is zero extended. If neither attribute is present, we can't make any assumptions. The clang frontend should always put signext on i32 function arguments to match the psABI.

Thanks for the detail.

Since we cannot make this assumption for the general case, then would it be reasonable to explicitly check for the case where the LHS is the result of an SEXT of an XOR?

topperc · 2025-03-12T22:34:31Z

ult of an SEXT of an XOR?

Yes. That's reasonable.

bababuck · 2025-03-13T19:30:03Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+  // Fold ((sext (xor X, C)), 0, eq/ne) -> ((sext(X), C, eq/ne)
+  if (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+    const SDValue LHS0 = LHS.getOperand(0);
+    if (IsFoldableXorEq(LHS0, RHS) && isa<ConstantSDNode>(LHS0.getOperand(1))) {


I added an extra constraint for the sign extension case that the XOR have one operand that is a constant. This keeps this change limited in scope so that it will only effect this specific case that results from the other changes in this patch.

bababuck · 2025-03-13T19:31:18Z

I have made changes according to the above conversation, this is ready for review again.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

lenary

You don't need unwind info in the tests

llvm/test/CodeGen/RISCV/select-constant-xor.ll

bababuck · 2025-03-13T20:50:15Z

Updated for latest suggestions.

bababuck · 2025-04-01T22:15:08Z

@topperc are there any more adjustments I should make before this can be merged?

topperc · 2025-04-01T22:23:15Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+  // If XOR is reused and has an immediate that will fit in XORI,
+  // do not fold.
+  auto IsXorImmediate = [](const SDValue &Op) -> bool {
+    if (const auto XorCnst = dyn_cast<ConstantSDNode>(Op))


const auto *XorCnst. LLVM Coding Standards don't want auto to hide that something is a pointer.

topperc · 2025-04-01T22:23:43Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+  // Fold (X(i1) ^ 1) == 0 -> X != 0
+  auto SingleBitOp = [&DAG](const SDValue &VarOp,
+                            const SDValue &ConstOp) -> bool {
+    if (const auto XorCnst = dyn_cast<ConstantSDNode>(ConstOp)) {


Same comment as above

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

mshockwave · 2025-04-01T22:24:51Z

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -17194,12 +17194,56 @@ static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
    return true;
  }

+  // If XOR is reused and has an immediate that will fit in XORI,
+  // do not fold.
+  auto IsXorImmediate = [](const SDValue &Op) -> bool {


~~lambda functions should following the normal function naming convention, which starts with lower case. ditto for other occurrences here.~~ nvm, this is not written.

In RISCV, modify the folding of (X ^ Y == 0) -> (X == Y) to account for cases where the (X ^ Y) will be re-used. Fixes llvm#130510.

bababuck · 2025-04-01T23:33:11Z

Addressed the prior comments, rebased onto latest main.

topperc

LGTM

github-actions · 2025-04-02T16:56:30Z

@bababuck Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

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bababuck · 2025-04-02T17:28:57Z

Thanks for the help everyone!

llvmbot added the backend:RISC-V label Mar 12, 2025

dtcxzyw requested review from asb, preames, topperc and wangpc-pp March 12, 2025 08:12

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topperc changed the title ~~Combine (X ^ Y) and (X == Y) where appropriate~~ [CodeGenPrepare][RISCV] Combine (X ^ Y) and (X == Y) where appropriate Mar 12, 2025

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bababuck added 2 commits April 1, 2025 15:33

Add new test that re-produces issue llvm#130510

1847d34

Combine (X ^ Y) and (X == Y) where appropriate

7433a60

In RISCV, modify the folding of (X ^ Y == 0) -> (X == Y) to account for cases where the (X ^ Y) will be re-used. Fixes llvm#130510.

bababuck force-pushed the rbuchner/130510 branch from fabb86c to 7433a60 Compare April 1, 2025 23:32

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mshockwave merged commit fa2a6d6 into llvm:main Apr 2, 2025
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[CodeGenPrepare][RISCV] Combine (X ^ Y) and (X == Y) where appropriate #130922

[CodeGenPrepare][RISCV] Combine (X ^ Y) and (X == Y) where appropriate #130922

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