[SPARC][MC] Add tests for VIS family instructions #130967
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Created using spr 1.3.5
Created using spr 1.3.5 [skip ci]
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) ChangesAlso fix up any mistakes/typos in instruction definitions. Patch is 41.81 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130967.diff 7 Files Affected:
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 3939f4ed94276..7d32cd8e5671b 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -201,6 +201,21 @@ class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
let Inst{4-0} = rs2;
}
+// SIAM instruction
+class F3_3_siam<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
+ string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
+ : F3<outs, ins, asmstr, pattern, itin> {
+ bits<3> siam_mode;
+
+ let op = opVal;
+ let op3 = op3val;
+ let rd = 0;
+ let rs1 = 0;
+ let Inst{13-5} = opfval; // fp opcode
+ let Inst{4-3} = 0;
+ let Inst{2-0} = siam_mode;
+}
+
// Shift by register rs2.
class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index c3b1fdf14d73e..0e8f743a83d5b 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -82,6 +82,8 @@ def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//
+def siam_mode : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;
+
def simm10 : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;
def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index bdefc70869d74..6d0f12da3afcf 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -12,71 +12,91 @@
// VIS Instruction Format.
class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
- list<dag> pattern>
+ list<dag> pattern = []>
: F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
-class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
+class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs,
+ list<dag> pattern = []>
: VISInstFormat<opfval,
(outs RC:$rd), (ins RC:$rs1, RC:$rs2),
- !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
+ !strconcat(OpcStr, " $rs1, $rs2, $rd"), pattern>;
// VIS Instruction with integer destination register.
-class VISInstID<bits<9> opfval, string OpcStr>
+class VISInstID<bits<9> opfval, string OpcStr, list<dag> pattern = []>
: VISInstFormat<opfval,
(outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
- !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
+ !strconcat(OpcStr, " $rs1, $rs2, $rd"), pattern>;
// For VIS Instructions with no operand.
let rd = 0, rs1 = 0, rs2 = 0 in
-class VISInst0<bits<9> opfval, string asmstr>
- : VISInstFormat<opfval, (outs), (ins), asmstr, []>;
+class VISInst0<bits<9> opfval, string asmstr, list<dag> pattern = []>
+ : VISInstFormat<opfval, (outs), (ins), asmstr, pattern>;
// For VIS Instructions with only rs1, rd operands.
let rs2 = 0 in
-class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
+class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs,
+ list<dag> pattern = []>
: VISInstFormat<opfval,
(outs RC:$rd), (ins RC:$rs1),
- !strconcat(OpcStr, " $rs1, $rd"), []>;
+ !strconcat(OpcStr, " $rs1, $rd"), pattern>;
// For VIS Instructions with only rs2, rd operands.
let rs1 = 0 in
-class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
+class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs,
+ list<dag> pattern = []>
: VISInstFormat<opfval,
(outs RC:$rd), (ins RC:$rs2),
- !strconcat(OpcStr, " $rs2, $rd"), []>;
+ !strconcat(OpcStr, " $rs2, $rd"), pattern>;
// For VIS Instructions with only rd operand.
let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
-class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
+class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs,
+ list<dag> pattern = []>
: VISInstFormat<opfval,
(outs RC:$rd), (ins RC:$f),
- !strconcat(OpcStr, " $rd"), []>;
+ !strconcat(OpcStr, " $rd"), pattern>;
// VIS 1 Instructions
let Predicates = [HasVIS] in {
def FPADD16 : VISInst<0b001010000, "fpadd16">;
-def FPADD16S : VISInst<0b001010001, "fpadd16s">;
+def FPADD16S : VISInst<0b001010001, "fpadd16s", FPRegs>;
def FPADD32 : VISInst<0b001010010, "fpadd32">;
-def FPADD32S : VISInst<0b001010011, "fpadd32s">;
+def FPADD32S : VISInst<0b001010011, "fpadd32s", FPRegs>;
def FPSUB16 : VISInst<0b001010100, "fpsub16">;
-def FPSUB16S : VISInst<0b001010101, "fpsub16S">;
+def FPSUB16S : VISInst<0b001010101, "fpsub16s", FPRegs>;
def FPSUB32 : VISInst<0b001010110, "fpsub32">;
-def FPSUB32S : VISInst<0b001010111, "fpsub32S">;
+def FPSUB32S : VISInst<0b001010111, "fpsub32s", FPRegs>;
def FPACK16 : VISInst2<0b000111011, "fpack16">;
def FPACK32 : VISInst <0b000111010, "fpack32">;
-def FPACKFIX : VISInst2<0b000111101, "fpackfix">;
-def FEXPAND : VISInst2<0b001001101, "fexpand">;
-def FPMERGE : VISInst <0b001001011, "fpmerge">;
-
-def FMUL8X16 : VISInst<0b000110001, "fmul8x16">;
-def FMUL8X16AU : VISInst<0b000110011, "fmul8x16au">;
-def FMUL8X16AL : VISInst<0b000110101, "fmul8x16al">;
+let rs1 = 0 in
+def FPACKFIX : VISInstFormat<0b000111101,
+ (outs FPRegs:$rd), (ins DFPRegs:$rs2), "fpackfix $rs2, $rd">;
+let rs1 = 0 in
+def FEXPAND : VISInstFormat<0b001001101,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs2), "fexpand $rs2, $rd">;
+def FPMERGE : VISInstFormat<0b001001011,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fpmerge $rs1, $rs2, $rd">;
+
+def FMUL8X16 : VISInstFormat<0b000110001,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, DFPRegs:$rs2),
+ "fmul8x16 $rs1, $rs2, $rd">;
+def FMUL8X16AU : VISInstFormat<0b000110011,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fmul8x16au $rs1, $rs2, $rd">;
+def FMUL8X16AL : VISInstFormat<0b000110101,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fmul8x16al $rs1, $rs2, $rd">;
def FMUL8SUX16 : VISInst<0b000110110, "fmul8sux16">;
def FMUL8ULX16 : VISInst<0b000110111, "fmul8ulx16">;
-def FMULD8SUX16 : VISInst<0b000111000, "fmuld8sux16">;
-def FMULD8ULX16 : VISInst<0b000111001, "fmuld8ulx16">;
+def FMULD8SUX16 : VISInstFormat<0b000111000,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fmuld8sux16 $rs1, $rs2, $rd">;
+def FMULD8ULX16 : VISInstFormat<0b000111001,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fmuld8ulx16 $rs1, $rs2, $rd">;
def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>;
def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>;
@@ -148,9 +168,11 @@ def SHUTDOWN : VISInst0<0b010000000, "shutdown">;
let Predicates = [HasVIS2] in {
def BMASK : VISInst<0b000011001, "bmask", I64Regs>;
-def BSHUFFLE : VISInst<0b000011100, "bshuffle">;
+def BSHUFFLE : VISInst<0b001001100, "bshuffle">;
-def SIAM : VISInst0<0b010000001, "siam">;
+let rd = 0, rs1 = 0 in
+def SIAM : F3_3_siam<0b10, 0b110110, 0b010000001, (outs),
+ (ins i32imm:$siam_mode), "siam $siam_mode", []>;
def EDGE8N : VISInst<0b000000001, "edge8n", I64Regs>;
def EDGE8LN : VISInst<0b000000011, "edge8ln", I64Regs>;
@@ -183,19 +205,19 @@ def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
def FCHKSM16 : VISInst<0b001000100, "fchksm16">;
def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fhadds $rs1, $rs2, $rd", []>;
def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fhaddd $rs1, $rs2, $rd", []>;
def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fhsubs $rs1, $rs2, $rd", []>;
def FHSUBD : F3_3<0b10, 0b110100, 0b001100110,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fhsubd $rs1, $rs2, $rd", []>;
def FLCMPS : VISInstFormat<0b101010001, (outs FCCRegs:$rd),
- (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (ins FPRegs:$rs1, FPRegs:$rs2),
"flcmps $rd, $rs1, $rs2", []>;
def FLCMPD : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
(ins DFPRegs:$rs1, DFPRegs:$rs2),
@@ -204,27 +226,27 @@ def FLCMPD : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
def FMEAN16 : VISInst<0b001000000, "fmean16">;
def FNADDS : F3_3<0b10, 0b110100, 0b001010001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fnadds $rs1, $rs2, $rd", []>;
def FNADDD : F3_3<0b10, 0b110100, 0b001010010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fnaddd $rs1, $rs2, $rd", []>;
def FNHADDS : F3_3<0b10, 0b110100, 0b001110001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fnhadds $rs1, $rs2, $rd", []>;
def FNHADDD : F3_3<0b10, 0b110100, 0b001110010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fnhaddd $rs1, $rs2, $rd", []>;
def FNMULS : F3_3<0b10, 0b110100, 0b001011001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
- "fnhadds $rs1, $rs2, $rd", []>;
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fnmuls $rs1, $rs2, $rd", []>;
def FNMULD : F3_3<0b10, 0b110100, 0b001011010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
- "fnhaddd $rs1, $rs2, $rd", []>;
+ "fnmuld $rs1, $rs2, $rd", []>;
def FNSMULD : F3_3<0b10, 0b110100, 0b001111001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
- "fnhadds $rs1, $rs2, $rd", []>;
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fnsmuld $rs1, $rs2, $rd", []>;
def FPADD64 : VISInst<0b001000010, "fpadd64">;
@@ -249,14 +271,14 @@ def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd),
(ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
def MOVWTOS : VISInstFormat<0b100011001, (outs DFPRegs:$rd),
- (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
+ (ins I64Regs:$rs2), "movwtos $rs2, $rd", []>;
def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd),
- (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
+ (ins I64Regs:$rs2), "movxtod $rs2, $rd", []>;
}
-def PDISTN : VISInst<0b000111111, "pdistn">;
+def PDISTN : VISInstID<0b000111111, "pdistn">;
def UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>;
def XMULX : VISInst<0b100010101, "xmulx", I64Regs>;
-def XMULXHI : VISInst<0b100010111, "xmulxhi", I64Regs>;
+def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>;
} // Predicates = [IsVIS3]
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-vis.txt b/llvm/test/MC/Disassembler/Sparc/sparc-vis.txt
new file mode 100644
index 0000000000000..56105fb41e8a5
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-vis.txt
@@ -0,0 +1,291 @@
+# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+vis,+vis2,+vis3 | FileCheck %s
+
+## VIS 1 instructions.
+
+# CHECK: fpadd16 %f0, %f2, %f4
+0x89,0xb0,0x0a,0x02
+# CHECK: fpadd16s %f1, %f3, %f5
+0x8b,0xb0,0x4a,0x23
+# CHECK: fpadd32 %f0, %f2, %f4
+0x89,0xb0,0x0a,0x42
+# CHECK: fpadd32s %f1, %f3, %f5
+0x8b,0xb0,0x4a,0x63
+# CHECK: fpsub16 %f0, %f2, %f4
+0x89,0xb0,0x0a,0x82
+# CHECK: fpsub16s %f1, %f3, %f5
+0x8b,0xb0,0x4a,0xa3
+# CHECK: fpsub32 %f0, %f2, %f4
+0x89,0xb0,0x0a,0xc2
+# CHECK: fpsub32s %f1, %f3, %f5
+0x8b,0xb0,0x4a,0xe3
+
+# CHECK: fpack16 %f0, %f2
+0x85,0xb0,0x07,0x60
+# CHECK: fpack32 %f0, %f2, %f4
+0x89,0xb0,0x07,0x42
+# CHECK: fpackfix %f0, %f3
+0x87,0xb0,0x07,0xa0
+# CHECK: fexpand %f1, %f2
+0x85,0xb0,0x09,0xa1
+# CHECK: fpmerge %f1, %f3, %f4
+0x89,0xb0,0x49,0x63
+
+# CHECK: fmul8x16 %f1, %f2, %f4
+0x89,0xb0,0x46,0x22
+# CHECK: fmul8x16au %f1, %f3, %f4
+0x89,0xb0,0x46,0x63
+# CHECK: fmul8x16al %f1, %f3, %f4
+0x89,0xb0,0x46,0xa3
+# CHECK: fmul8sux16 %f0, %f2, %f4
+0x89,0xb0,0x06,0xc2
+# CHECK: fmul8ulx16 %f0, %f2, %f4
+0x89,0xb0,0x06,0xe2
+# CHECK: fmuld8sux16 %f1, %f3, %f4
+0x89,0xb0,0x47,0x03
+# CHECK: fmuld8ulx16 %f1, %f3, %f4
+0x89,0xb0,0x47,0x23
+
+# CHECK: alignaddr %o0, %o1, %o2
+0x95,0xb2,0x03,0x09
+# CHECK: alignaddrl %o0, %o1, %o2
+0x95,0xb2,0x03,0x49
+# CHECK: faligndata %f0, %f2, %f4
+0x89,0xb0,0x09,0x02
+
+# CHECK: fzero %f0
+0x81,0xb0,0x0c,0x00
+# CHECK: fzeros %f1
+0x83,0xb0,0x0c,0x20
+# CHECK: fone %f0
+0x81,0xb0,0x0f,0xc0
+# CHECK: fones %f1
+0x83,0xb0,0x0f,0xe0
+# CHECK: fsrc1 %f0, %f2
+0x85,0xb0,0x0e,0x80
+# CHECK: fsrc1s %f1, %f3
+0x87,0xb0,0x4e,0xa0
+# CHECK: fsrc2 %f0, %f2
+0x85,0xb0,0x0f,0x00
+# CHECK: fsrc2s %f1, %f3
+0x87,0xb0,0x0f,0x21
+# CHECK: fnot1 %f0, %f2
+0x85,0xb0,0x0d,0x40
+# CHECK: fnot1s %f1, %f3
+0x87,0xb0,0x4d,0x60
+# CHECK: fnot2 %f0, %f2
+0x85,0xb0,0x0c,0xc0
+# CHECK: fnot2s %f1, %f3
+0x87,0xb0,0x0c,0xe1
+# CHECK: for %f0, %f2, %f4
+0x89,0xb0,0x0f,0x82
+# CHECK: fors %f1, %f3, %f5
+0x8b,0xb0,0x4f,0xa3
+# CHECK: fnor %f0, %f2, %f4
+0x89,0xb0,0x0c,0x42
+# CHECK: fnors %f1, %f3, %f5
+0x8b,0xb0,0x4c,0x63
+# CHECK: fand %f0, %f2, %f4
+0x89,0xb0,0x0e,0x02
+# CHECK: fands %f1, %f3, %f5
+0x8b,0xb0,0x4e,0x23
+# CHECK: fnand %f0, %f2, %f4
+0x89,0xb0,0x0d,0xc2
+# CHECK: fnands %f1, %f3, %f5
+0x8b,0xb0,0x4d,0xe3
+# CHECK: fxor %f0, %f2, %f4
+0x89,0xb0,0x0d,0x82
+# CHECK: fxors %f1, %f3, %f5
+0x8b,0xb0,0x4d,0xa3
+# CHECK: fxnor %f0, %f2, %f4
+0x89,0xb0,0x0e,0x42
+# CHECK: fxnors %f1, %f3, %f5
+0x8b,0xb0,0x4e,0x63
+
+# CHECK: fornot1 %f0, %f2, %f4
+0x89,0xb0,0x0f,0x42
+# CHECK: fornot1s %f1, %f3, %f5
+0x8b,0xb0,0x4f,0x63
+# CHECK: fornot2 %f0, %f2, %f4
+0x89,0xb0,0x0e,0xc2
+# CHECK: fornot2s %f1, %f3, %f5
+0x8b,0xb0,0x4e,0xe3
+# CHECK: fandnot1 %f0, %f2, %f4
+0x89,0xb0,0x0d,0x02
+# CHECK: fandnot1s %f1, %f3, %f5
+0x8b,0xb0,0x4d,0x23
+# CHECK: fandnot2 %f0, %f2, %f4
+0x89,0xb0,0x0c,0x82
+# CHECK: fandnot2s %f1, %f3, %f5
+0x8b,0xb0,0x4c,0xa3
+
+# CHECK: fcmpgt16 %f0, %f2, %o0
+0x91,0xb0,0x05,0x02
+# CHECK: fcmpgt32 %f0, %f2, %o0
+0x91,0xb0,0x05,0x82
+# CHECK: fcmple16 %f0, %f2, %o0
+0x91,0xb0,0x04,0x02
+# CHECK: fcmple32 %f0, %f2, %o0
+0x91,0xb0,0x04,0x82
+# CHECK: fcmpne16 %f0, %f2, %o0
+0x91,0xb0,0x04,0x42
+# CHECK: fcmpne32 %f0, %f2, %o0
+0x91,0xb0,0x04,0xc2
+# CHECK: fcmpeq16 %f0, %f2, %o0
+0x91,0xb0,0x05,0x42
+# CHECK: fcmpeq32 %f0, %f2, %o0
+0x91,0xb0,0x05,0xc2
+
+# CHECK: edge8 %o0, %o1, %o2
+0x95,0xb2,0x00,0x09
+# CHECK: edge8l %o0, %o1, %o2
+0x95,0xb2,0x00,0x49
+# CHECK: edge16 %o0, %o1, %o2
+0x95,0xb2,0x00,0x89
+# CHECK: edge16l %o0, %o1, %o2
+0x95,0xb2,0x00,0xc9
+# CHECK: edge32 %o0, %o1, %o2
+0x95,0xb2,0x01,0x09
+# CHECK: edge32l %o0, %o1, %o2
+0x95,0xb2,0x01,0x49
+
+# CHECK: pdist %f0, %f2, %f4
+0x89,0xb0,0x07,0xc2
+
+# CHECK: array8 %o0, %o1, %o2
+0x95,0xb2,0x02,0x09
+# CHECK: array16 %o0, %o1, %o2
+0x95,0xb2,0x02,0x49
+# CHECK: array32 %o0, %o1, %o2
+0x95,0xb2,0x02,0x89
+
+# CHECK: shutdown
+0x81,0xb0,0x10,0x00
+
+## VIS 2 instructions.
+
+# CHECK: bmask %o0, %o1, %o2
+0x95,0xb2,0x03,0x29
+# CHECK: bshuffle %f0, %f2, %f4
+0x89,0xb0,0x09,0x82
+
+# CHECK: siam 0
+0x81,0xb0,0x10,0x20
+# CHECK: siam 1
+0x81,0xb0,0x10,0x21
+# CHECK: siam 2
+0x81,0xb0,0x10,0x22
+# CHECK: siam 3
+0x81,0xb0,0x10,0x23
+# CHECK: siam 4
+0x81,0xb0,0x10,0x24
+# CHECK: siam 5
+0x81,0xb0,0x10,0x25
+# CHECK: siam 6
+0x81,0xb0,0x10,0x26
+# CHECK: siam 7
+0x81,0xb0,0x10,0x27
+
+# CHECK: edge8n %o0, %o1, %o2
+0x95,0xb2,0x00,0x29
+# CHECK: edge8ln %o0, %o1, %o2
+0x95,0xb2,0x00,0x69
+# CHECK: edge16n %o0, %o1, %o2
+0x95,0xb2,0x00,0xa9
+# CHECK: edge16ln %o0, %o1, %o2
+0x95,0xb2,0x00,0xe9
+# CHECK: edge32n %o0, %o1, %o2
+0x95,0xb2,0x01,0x29
+# CHECK: edge32ln %o0, %o1, %o2
+0x95,0xb2,0x01,0x69
+
+## VIS 3 instructions.
+
+# CHECK: addxc %o0, %o1, %o2
+0x95,0xb2,0x02,0x29
+# CHECK: addxccc %o0, %o1, %o2
+0x95,0xb2,0x02,0x69
+
+# CHECK: cmask8 %o0
+0x81,0xb0,0x03,0x68
+# CHECK: cmask16 %o0
+0x81,0xb0,0x03,0xa8
+# CHECK: cmask32 %o0
+0x81,0xb0,0x03,0xe8
+
+# CHECK: fchksm16 %f0, %f2, %f4
+0x89,0xb0,0x08,0x82
+# CHECK: fmean16 %f0, %f2, %f4
+0x89,0xb0,0x08,0x02
+
+# CHECK: fhadds %f1, %f3, %f5
+0x8b,0xa0,0x4c,0x23
+# CHECK: fhaddd %f0, %f2, %f4
+0x89,0xa0,0x0c,0x42
+# CHECK: fhsubs %f1, %f3, %f5
+0x8b,0xa0,0x4c,0xa3
+# CHECK: fhsubd %f0, %f2, %f4
+0x89,0xa0,0x0c,0xc2
+# CHECK: flcmps %fcc0, %f3, %f5
+0x81,0xb0,0xea,0x25
+# CHECK: flcmpd %fcc0, %f2, %f4
+0x81,0xb0,0xaa,0x44
+
+# CHECK: fnadds %f1, %f3, %f5
+0x8b,0xa0,0x4a,0x23
+# CHECK: fnaddd %f0, %f2, %f4
+0x89,0xa0,0x0a,0x42
+# CHECK: fnhadds %f1, %f3, %f5
+0x8b,0xa0,0x4e,0x23
+# CHECK: fnhaddd %f0, %f2, %f4
+0x89,0xa0,0x0e,0x42
+
+# CHECK: fnmuls %f1, %f3, %f5
+0x8b,0xa0,0x4b,0x23
+# CHECK: fnmuld %f0, %f2, %f4
+0x89,0xa0,0x0b,0x42
+# CHECK: fnsmuld %f1, %f3, %f4
+0x89,0xa0,0x4f,0x23
+
+# CHECK: fpadd64 %f0, %f2, %f4
+0x89,0xb0,0x08,0x42
+
+# CHECK: fsll16 %f0, %f2, %f4
+0x89,0xb0,0x04,0x22
+# CHECK: fsrl16 %f0, %f2, %f4
+0x89,0xb0,0x04,0x62
+# CHECK: fsll32 %f0, %f2, %f4
+0x89,0xb0,0x04,0xa2
+# CHECK: fsrl32 %f0, %f2, %f4
+0x89,0xb0,0x04,0xe2
+# CHECK: fslas16 %f0, %f2, %f4
+0x89,0xb0,0x05,0x22
+# CHECK: fsra16 %f0, %f2, %f4
+0x89,0xb0,0x05,0x62
+# CHECK: fslas32 %f0, %f2, %f4
+0x89,0xb0,0x05,0xa2
+# CHECK: fsra32 %f0, %f2, %f4
+0x89,0xb0,0x05,0xe2
+
+# CHECK: lzcnt %o0, %o1
+0x93,0xb0,0x02,0xe8
+
+# CHECK: movstosw %f0, %o0
+0x91,0xb0,0x22,0x60
+# CHECK: movstouw %f0, %o0
+0x91,0xb0,0x22,0x20
+# CHECK: movdtox %f0, %o0
+0x91,0xb0,0x22,0x00
+# CHECK: movwtos %o0, %f0
+0x81,0xb0,0x23,0x28
+# CHECK: movxtod %o0, %f0
+0x81,0xb0,0x23,0x08
+
+# CHECK: pdistn %f0, %f2, %o0
+0x91,0xb0,0x07,0xe2
+
+# CHECK: umulxhi %o0, %o1, %o2
+0x95,0xb2,0x02,0xc9
+# CHECK: xmulx %o0, %o1, %o2
+0x95,0xb2,0x22,0xa9
+# CHECK: xmulxhi %o0, %o1, %o2
+0x95,0xb2,0x22,0xc9
diff --git a/llvm/test/MC/Sparc/sparc-vis.s b/llvm/test/MC/Sparc/sparc-vis.s
index 77e1ab1432eed..bf01da19293d0 100644
--- a/llvm/test/MC/Sparc/sparc-vis.s
+++ b/llvm/test/MC/Sparc/sparc-vis.s
@@ -1,4 +1,226 @@
-! RUN: llvm-mc %s -triple=sparcv9 -mcpu=niagara -show-encoding | FileCheck %s
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis -show-encoding | FileCheck %s --check-prefixes=VIS
- ! CHECK: fzeros %f31 ! encoding: [0xbf,0xb0,0x0c,0x20]
- fzeros %f31
+!! VIS 1 instructions.
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpadd16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0a,0x02]
+fpadd16 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpadd16s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4a,0x23]
+fpadd16s %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpadd32 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0a,0x42]
+fpadd32 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpadd32s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4a,0x63]
+fpadd32s %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feat...
[truncated]
|
Created using spr 1.3.5
Created using spr 1.3.5
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Ping? |
s-barannikov
approved these changes
Mar 22, 2025
MaskRay
reviewed
Mar 22, 2025
Created using spr 1.3.5
Created using spr 1.3.5 [skip ci]
Created using spr 1.3.5
|
Ping? Okay if I merge it now? |
Created using spr 1.3.5
koachan
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Apr 3, 2025
Also fix up any mistakes/typos in instruction definitions. Reviewers: rorth, s-barannikov, brad0, MaskRay Reviewed By: s-barannikov Pull Request: llvm/llvm-project#130967
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Also fix up any mistakes/typos in instruction definitions.