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Mar 13, 2025
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AMDGPU: Replace some test i32 undef uses with poison #131092

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
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Expand Up @@ -581,7 +581,7 @@ done:

; OPT-LABEL: @test_sink_local_small_offset_cmpxchg_i32(
; OPT: %sunkaddr = getelementptr i8, ptr addrspace(3) %in, i32 28
; OPT: %tmp1.struct = cmpxchg ptr addrspace(3) %sunkaddr, i32 undef, i32 2 seq_cst monotonic
; OPT: %tmp1.struct = cmpxchg ptr addrspace(3) %sunkaddr, i32 poison, i32 2 seq_cst monotonic
define amdgpu_kernel void @test_sink_local_small_offset_cmpxchg_i32(ptr addrspace(3) %out, ptr addrspace(3) %in) {
entry:
%out.gep = getelementptr i32, ptr addrspace(3) %out, i32 999999
Expand All @@ -591,7 +591,7 @@ entry:
br i1 %tmp0, label %endif, label %if

if:
%tmp1.struct = cmpxchg ptr addrspace(3) %in.gep, i32 undef, i32 2 seq_cst monotonic
%tmp1.struct = cmpxchg ptr addrspace(3) %in.gep, i32 poison, i32 2 seq_cst monotonic
%tmp1 = extractvalue { i32, i1 } %tmp1.struct, 0
br label %endif

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/commute-shifts.ll
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Expand Up @@ -30,7 +30,7 @@ define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
; VI-NEXT: ; return to shader part epilog
bb:
%tmp = fptosi float %arg0 to i32
%tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> poison, i32 0, i32 0)
%tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 poison, <8 x i32> poison, i32 0, i32 0)
%tmp2.f = extractelement <4 x float> %tmp1, i32 0
%tmp2 = bitcast float %tmp2.f to i32
%tmp3 = and i32 %tmp, 7
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
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Expand Up @@ -306,7 +306,7 @@ define amdgpu_vs float @load_addr_no_fold(ptr addrspace(6) inreg noalias %p0) #0
define amdgpu_vs float @vgpr_arg_src(ptr addrspace(6) %arg) {
main_body:
%tmp9 = load ptr addrspace(8), ptr addrspace(6) %arg
%tmp10 = call nsz float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp9, i32 undef, i32 0, i32 0, i32 0) #1
%tmp10 = call nsz float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp9, i32 poison, i32 0, i32 0, i32 0) #1
ret float %tmp10
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
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Expand Up @@ -204,7 +204,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
%40 = fmul reassoc nnan nsz arcp contract afn float %39, 0x3F847AE140000000
%41 = fadd reassoc nnan nsz arcp contract afn float %40, 0x3F947AE140000000
%.i2415 = fmul reassoc nnan nsz arcp contract afn float %.i2407, %41
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> poison, i32 0, i32 0)
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 poison, i32 poison, i32 0, <8 x i32> poison, i32 0, i32 0)
%.i2521 = extractelement <3 x float> %42, i32 2
%43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
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Expand Up @@ -25,11 +25,11 @@ define amdgpu_hs void @main(ptr addrspace(6) inreg %arg) {
; GCN-NEXT: BUFFER_STORE_DWORDX3_OFFEN_exact killed [[COPY4]], [[COPY5]], [[DEF3]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s96) into `ptr addrspace(8) poison`, align 1, addrspace 8)
; GCN-NEXT: S_ENDPGM 0
main_body:
%tmp25 = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) poison, i32 undef, i32 0, i32 0)
%tmp25 = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) poison, i32 poison, i32 0, i32 0)
%tmp27 = bitcast <4 x float> %tmp25 to <16 x i8>
%tmp28 = shufflevector <16 x i8> %tmp27, <16 x i8> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
%tmp29 = bitcast <12 x i8> %tmp28 to <3 x i32>
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %tmp29, ptr addrspace(8) poison, i32 undef, i32 0, i32 0) #3
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %tmp29, ptr addrspace(8) poison, i32 poison, i32 0, i32 0) #3
ret void
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
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Expand Up @@ -11,7 +11,7 @@
; GCN: IMAGE_LOAD_V4_V2
define amdgpu_cs void @_amdgpu_cs_main(i32 %dummy) local_unnamed_addr #0 {
.entry:
%unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> poison, i32 0, i32 0) #3
%unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 poison, i32 poison, <8 x i32> poison, i32 0, i32 0) #3
call void asm sideeffect ";", "" () #0
ret void
}
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
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Expand Up @@ -75,7 +75,7 @@ define amdgpu_kernel void @indirect_call_known_no_special_inputs() {
bb:
%cond = load i1, ptr addrspace(4) null
%tmp = select i1 %cond, ptr @wobble, ptr @snork
call void %tmp(ptr poison, i32 undef, ptr poison)
call void %tmp(ptr poison, i32 poison, ptr poison)
ret void
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
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Expand Up @@ -185,7 +185,7 @@ sw.bb10:
; GCN-DAG: v_readlane_b32 s30, [[CSR_VGPR]],
; GCN: s_waitcnt vmcnt(0)
; GCN: s_setpc_b64 s[30:31]
call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 undef, i8 undef, float poison, float poison, float poison, i1 undef, <4 x i32> poison, float poison, i32 undef, i1 undef, i1 undef, i1 undef, float poison, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 undef, i1 undef, i32 undef, i64 undef, i32 undef)
call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 poison, i8 undef, float poison, float poison, float poison, i1 undef, <4 x i32> poison, float poison, i32 poison, i1 undef, i1 undef, i1 undef, float poison, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 poison, i1 undef, i32 poison, i64 undef, i32 poison)
ret void
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll
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Expand Up @@ -9,7 +9,7 @@ declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1
; NOPRIM: exp invalid_target_20 v0, off, off, off done{{$}}
; PRIM: {{exp|export}} prim v0, off, off, off done{{$}}
define amdgpu_gs void @test_export_prim_i32(i32 inreg %a) #0 {
call void @llvm.amdgcn.exp.i32(i32 20, i32 1, i32 %a, i32 undef, i32 undef, i32 undef, i1 true, i1 false)
call void @llvm.amdgcn.exp.i32(i32 20, i32 1, i32 %a, i32 poison, i32 poison, i32 poison, i1 true, i1 false)
ret void
}

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14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
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Expand Up @@ -22,8 +22,8 @@ define amdgpu_kernel void @undef_i32() #0 {
; GFX12-NEXT: export pos0 off, off, off, off row_en
; GFX12-NEXT: export pos1 off, off, off, off done row_en
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i1 false, i32 0)
call void @llvm.amdgcn.exp.row.i32(i32 13, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i1 true, i32 0)
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i1 false, i32 0)
call void @llvm.amdgcn.exp.row.i32(i32 13, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i1 true, i32 0)
ret void
}

Expand Down Expand Up @@ -62,8 +62,8 @@ define amdgpu_kernel void @zero_i32() #0 {
; GFX12-NEXT: export pos0 v0, v0, v0, off row_en
; GFX12-NEXT: export pos1 v0, v0, v0, off done row_en
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 7, i32 0, i32 0, i32 0, i32 undef, i1 false, i32 0)
call void @llvm.amdgcn.exp.row.i32(i32 13, i32 7, i32 0, i32 0, i32 0, i32 undef, i1 true, i32 0)
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 7, i32 0, i32 0, i32 0, i32 poison, i1 false, i32 0)
call void @llvm.amdgcn.exp.row.i32(i32 13, i32 7, i32 0, i32 0, i32 0, i32 poison, i1 true, i32 0)
ret void
}

Expand Down Expand Up @@ -103,7 +103,7 @@ define amdgpu_kernel void @id_i32() #0 {
; GFX12-NEXT: export pos0 v0, off, off, off done row_en
; GFX12-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x()
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 undef, i32 undef, i32 undef, i1 true, i32 0)
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 poison, i32 poison, i32 poison, i1 true, i32 0)
ret void
}

Expand All @@ -126,7 +126,7 @@ define amdgpu_kernel void @id_arg_i32(i32 %row) #0 {
; GFX12-NEXT: export pos0 v0, off, off, off done row_en
; GFX12-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x()
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 undef, i32 undef, i32 undef, i1 true, i32 %row)
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 poison, i32 poison, i32 poison, i1 true, i32 %row)
ret void
}

Expand Down Expand Up @@ -170,6 +170,6 @@ define amdgpu_kernel void @id_row_i32() #0 {
; GFX12-GISEL-NEXT: export pos0 v1, off, off, off done row_en
; GFX12-GISEL-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x()
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 99, i32 undef, i32 undef, i32 undef, i1 true, i32 %id)
call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 99, i32 poison, i32 poison, i32 poison, i1 true, i32 %id)
ret void
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
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Expand Up @@ -141,7 +141,7 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
; GFX12-NEXT: ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
bb:
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 undef)
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 poison)
%i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %arg, i32 %arg1, i32 0, i32 0, i32 0)
%i3 = bitcast <3 x half> %i2 to <3 x i16>
%i4 = extractelement <3 x i16> %i3, i32 1
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
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Expand Up @@ -112,7 +112,7 @@ define amdgpu_gs void @main(ptr addrspace(8) %arg, i32 %arg1) {
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
; GFX11-NEXT: ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
bb:
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 undef)
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 poison)
%i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v3f16(ptr addrspace(8) %arg, i32 %arg1, i32 0, i32 0, i32 0)
%i3 = bitcast <3 x half> %i2 to <3 x i16>
%i4 = extractelement <3 x i16> %i3, i32 1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
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Expand Up @@ -42,7 +42,7 @@ define i32 @test_s_wqm_constant_undef_i32() {
; GFX11-NEXT: s_wqm_b32 s0, s0
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 undef)
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 poison)
ret i32 %br
}

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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
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Expand Up @@ -46,7 +46,7 @@ loop:
br i1 %tmp27, label %then, label %endif

then: ; preds = %bb
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 poison, i32 0)
br label %endif

endif: ; preds = %bb28, %bb
Expand Down Expand Up @@ -85,7 +85,7 @@ loop:
%tmp23phi = phi i32 [ %tmp23, %loop ], [ 0, %entry ]
%tmp23 = add nuw i32 %tmp23phi, 1
%tmp27 = icmp ult i32 %arg, %tmp23
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 poison, i32 0)
br i1 %tmp27, label %loop, label %loopexit

loopexit:
Expand Down Expand Up @@ -136,7 +136,7 @@ loop:
br i1 %tmp27, label %then, label %endif

then: ; preds = %bb
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 poison, i32 0)
br label %endif

endif: ; preds = %bb28, %bb
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/merge-load-store.mir
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Expand Up @@ -34,8 +34,8 @@
bb:
%tmp1 = load i32, i32 addrspace(3)* getelementptr inbounds ([256 x i32], [256 x i32] addrspace(3)* @lds0, i32 0, i32 0), align 4
%0 = and i32 %tmp1, 255
%tmp3 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 undef), align 4
%tmp6 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 undef), align 4
%tmp3 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 poison), align 4
%tmp6 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 poison), align 4
%tmp7 = tail call i32 asm "v_or_b32 $0, 0, $1", "=v,v"(i32 %tmp6) #1
%tmp10 = lshr i32 %tmp7, 16
%tmp11 = and i32 %tmp10, 255
Expand All @@ -48,7 +48,7 @@
%tmp20 = and i32 %tmp19, 255
%tmp21 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 %tmp20
%tmp22 = load i32, i32 addrspace(3)* %tmp21, align 4
%tmp24 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 undef), align 4
%tmp24 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 poison), align 4
%tmp25 = xor i32 %tmp22, %tmp24
%tmp26 = and i32 %tmp25, -16777216
%tmp28 = or i32 %0, %tmp26
Expand Down Expand Up @@ -129,12 +129,12 @@ body: |
bb.0:
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vgpr_32 = DS_READ_B32 %1, 3072, 0, implicit $m0, implicit $exec :: (dereferenceable load (s32) from `i32 addrspace(3)* getelementptr inbounds ([256 x i32], [256 x i32] addrspace(3)* @lds0, i32 0, i32 0)`, addrspace 3)
%3:vgpr_32 = DS_READ_B32 %1, 2048, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 undef)`, addrspace 3)
%4:vgpr_32 = DS_READ_B32 %1, 1024, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 undef)`, addrspace 3)
%3:vgpr_32 = DS_READ_B32 %1, 2048, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 poison)`, addrspace 3)
%4:vgpr_32 = DS_READ_B32 %1, 1024, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 poison)`, addrspace 3)
INLINEASM &"v_or_b32 $0, 0, $1", 32, 327690, def %0, 327689, %4
%5:vgpr_32 = DS_READ_B32 %0, 2048, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp12, addrspace 3)
%6:vgpr_32 = DS_READ_B32 %5, 2048, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp21, addrspace 3)
%7:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 undef)`, addrspace 3)
%7:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 poison)`, addrspace 3)
S_SETPC_B64_return undef $sgpr30_sgpr31, implicit %6, implicit %7

...
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
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Expand Up @@ -22,7 +22,7 @@ define amdgpu_vs float @test_idxen(ptr addrspace(4) inreg %base, i32 %i) {
main_body:
%ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
%tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i32 0, i32 0)
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 poison, i32 0, i32 0, i32 0)
ret float %tmp7
}

Expand All @@ -32,7 +32,7 @@ define amdgpu_vs float @test_offen(ptr addrspace(4) inreg %base, i32 %i) {
main_body:
%ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
%tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
%tmp7 = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i32 0)
%tmp7 = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %tmp2, i32 poison, i32 0, i32 0)
ret float %tmp7
}

Expand All @@ -42,7 +42,7 @@ define amdgpu_vs float @test_both(ptr addrspace(4) inreg %base, i32 %i) {
main_body:
%ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
%tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i32 0, i32 0)
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 poison, i32 poison, i32 0, i32 0)
ret float %tmp7
}

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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
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Expand Up @@ -19,7 +19,7 @@ define amdgpu_vs float @test_idxen(ptr addrspace(4) inreg %base, i32 %i) {
main_body:
%ptr = getelementptr ptr addrspace(8), ptr addrspace(4) %base, i32 %i
%tmp2 = load ptr addrspace(8), ptr addrspace(4) %ptr, align 32
%tmp7 = call float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 undef, i32 0, i32 0, i32 0)
%tmp7 = call float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 poison, i32 0, i32 0, i32 0)
ret float %tmp7
}

Expand All @@ -29,7 +29,7 @@ define amdgpu_vs float @test_offen(ptr addrspace(4) inreg %base, i32 %i) {
main_body:
%ptr = getelementptr ptr addrspace(8), ptr addrspace(4) %base, i32 %i
%tmp2 = load ptr addrspace(8), ptr addrspace(4) %ptr, align 32
%tmp7 = call float @llvm.amdgcn.raw.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 undef, i32 0, i32 0)
%tmp7 = call float @llvm.amdgcn.raw.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 poison, i32 0, i32 0)
ret float %tmp7
}

Expand All @@ -39,7 +39,7 @@ define amdgpu_vs float @test_both(ptr addrspace(4) inreg %base, i32 %i) {
main_body:
%ptr = getelementptr ptr addrspace(8), ptr addrspace(4) %base, i32 %i
%tmp2 = load ptr addrspace(8), ptr addrspace(4) %ptr, align 32
%tmp7 = call float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 undef, i32 undef, i32 0, i32 0)
%tmp7 = call float @llvm.amdgcn.struct.ptr.buffer.load.format.f32(ptr addrspace(8) %tmp2, i32 poison, i32 poison, i32 0, i32 0)
ret float %tmp7
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
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Expand Up @@ -92,7 +92,7 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; PEI-GFX90A-NEXT: GLOBAL_STORE_DWORDX2 undef renamable $vgpr0_vgpr1, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec :: (volatile store (s64) into `ptr addrspace(1) poison`, addrspace 1)
; PEI-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef renamable $vgpr0_vgpr1, killed renamable $agpr0_agpr1_agpr2_agpr3, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; PEI-GFX90A-NEXT: S_ENDPGM 0
call void asm sideeffect "; use $0", "a" (i32 undef)
call void asm sideeffect "; use $0", "a" (i32 poison)
%v0 = call <4 x i32> asm sideeffect "; def $0", "=v" ()
%v1 = call <2 x i32> asm sideeffect "; def $0", "=v" ()
%mai = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 2, <4 x i32> %arg, i32 0, i32 0, i32 0)
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