[RISCV] Add Zilsd and Zclsd Extensions

[dong-miao]

This commit adds the Load/Store pair instructions (Zilsd) and Compressed Load/Store pair instructions (Zclsd).
Specification link.

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[topperc]

The conflict with Zcf needs to be checked in RISCVISAInfo::checkDependency in llvm/lib/TargetParser/RISCVISAInfo.cpp

[lenary]

This is not yet resolved, the check here should be exactly the following:

Suggested change

	def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd() && !Subtarget->hasStdExtZcf()">,
	def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd()">,

[dong-miao]

When I tested with sudo ninja - C build check-llvm locally, there were two testing errors that I couldn't solve. For rv32zclsd-valid. s, errors may occur during the disassembly process because the test file does not report errors when I remove Check-ASM-AND-OBJ.
Error record.txt

[topperc]

This should fix your failures

diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 214378d4b554..59ab59703ac7 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -763,7 +763,7 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
   TRY_TO_DECODE_AND_ADD_SP(true, DecoderTableRISCV32Only_16,
                            "RISCV32Only_16 (16-bit Instruction)");
   // Zc* instructions incompatible with Zcf or Zcd.
-  TRY_TO_DECODE(true, DecoderTableZcOverlap16,
+  TRY_TO_DECODE_AND_ADD_SP(true, DecoderTableZcOverlap16,
                 "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)");
 
   return MCDisassembler::Fail;
diff --git a/llvm/test/MC/RISCV/rv64c-valid.s b/llvm/test/MC/RISCV/rv64c-valid.s
index f8736e5d5453..b0d2bc576be9 100644
--- a/llvm/test/MC/RISCV/rv64c-valid.s
+++ b/llvm/test/MC/RISCV/rv64c-valid.s
@@ -19,26 +19,26 @@
 
 # TODO: more exhaustive testing of immediate encoding.
 
-# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
-# CHECK-ASM: encoding: [0x82,0x60]
+# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp)
+# CHECK-ASM: encoding: [0x02,0x64]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set{{$}}
-c.ldsp ra, 0(sp)
-# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp)
-# CHECK-ASM: encoding: [0x86,0xff]
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' (Compressed Load/Store pair instructions){{$}}
+c.ldsp s0, 0(sp)
+# CHECK-ASM-AND-OBJ: c.sdsp s2, 504(sp)
+# CHECK-ASM: encoding: [0xca,0xff]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set{{$}}
-c.sdsp ra, 504(sp)
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' (Compressed Load/Store pair instructions){{$}}
+c.sdsp s2, 504(sp)
 # CHECK-ASM-AND-OBJ: c.ld a4, 0(a3)
 # CHECK-ASM: encoding: [0x98,0x62]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set{{$}}
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' (Compressed Load/Store pair instructions){{$}}
 c.ld a4, 0(a3)
-# CHECK-ASM-AND-OBJ: c.sd a5, 248(a3)
-# CHECK-ASM: encoding: [0xfc,0xfe]
+# CHECK-ASM-AND-OBJ: c.sd a2, 248(a3)
+# CHECK-ASM: encoding: [0xf0,0xfe]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
-# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set{{$}}
-c.sd a5, 248(a3)
+# CHECK-NO-RV64:  error: instruction requires the following: 'Zclsd' (Compressed Load/Store pair instructions){{$}}
+c.sd a2, 248(a3)
 
 # CHECK-ASM-AND-OBJ: c.subw a3, a4
 # CHECK-ASM: encoding: [0x99,0x9e]

[wangpc-pp]

Please add a ReleaseNote.

[lenary]

This is not yet resolved, the check here should be exactly the following:

Suggested change

	def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd() && !Subtarget->hasStdExtZcf()">,
	def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd()">,

[topperc]

LGTM

[topperc]

LGTM. do you need someone to merge this?

[dong-miao]

do you need someone to merge this?

Yes,Please help me merge.

[lenary]

LGTM. Thanks!