Skip to content

AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests #131095

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Mar 14, 2025
Merged

AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests #131095

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
64 changes: 32 additions & 32 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
View file
Open in desktop

Large diffs are not rendered by default.

8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32() #0 {
; CHECK-LABEL: name: test_gfx_call_external_void_func_struct_i8_i32
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) undef`, addrspace 4)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load (s8) from %ir.ptr0, align 4, addrspace 1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)
Expand All @@ -81,7 +81,7 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32() #0 {
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
%ptr0 = load ptr addrspace(1), ptr addrspace(4) undef
%ptr0 = load ptr addrspace(1), ptr addrspace(4) poison
%val = load { i8, i32 }, ptr addrspace(1) %ptr0
call amdgpu_gfx void @external_gfx_void_func_struct_i8_i32({ i8, i32 } %val)
ret void
Expand All @@ -91,7 +91,7 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() #
; CHECK-LABEL: name: test_gfx_call_external_void_func_struct_i8_i32_inreg
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) undef`, addrspace 4)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load (s8) from %ir.ptr0, align 4, addrspace 1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)
Expand All @@ -109,7 +109,7 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() #
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32_inreg, csr_amdgpu_si_gfx, implicit $sgpr4, implicit $sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
%ptr0 = load ptr addrspace(1), ptr addrspace(4) undef
%ptr0 = load ptr addrspace(1), ptr addrspace(4) poison
%val = load { i8, i32 }, ptr addrspace(1) %ptr0
call amdgpu_gfx void @external_gfx_void_func_struct_i8_i32_inreg({ i8, i32 } inreg %val)
ret void
Expand Down
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
View file
Open in desktop

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -826,7 +826,7 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX90A-NEXT: .LBB3_12: ; %DummyReturnBlock
; GFX90A-NEXT: s_endpgm
bb:
%i = load volatile i16, ptr addrspace(4) undef, align 2
%i = load volatile i16, ptr addrspace(4) poison, align 2
%i6 = zext i16 %i to i64
%i7 = udiv i32 %arg1, %arg2
%i8 = zext i32 %i7 to i64
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,17 +7,17 @@
; ALL: SGPRBlocks: 1
; ALL: NumSGPRsForWavesPerEU: 10
define amdgpu_kernel void @max_10_sgprs() #0 {
%one = load volatile i32, ptr addrspace(4) undef
%two = load volatile i32, ptr addrspace(4) undef
%three = load volatile i32, ptr addrspace(4) undef
%four = load volatile i32, ptr addrspace(4) undef
%five = load volatile i32, ptr addrspace(4) undef
%six = load volatile i32, ptr addrspace(4) undef
%seven = load volatile i32, ptr addrspace(4) undef
%eight = load volatile i32, ptr addrspace(4) undef
%nine = load volatile i32, ptr addrspace(4) undef
%ten = load volatile i32, ptr addrspace(4) undef
%eleven = load volatile i32, ptr addrspace(4) undef
%one = load volatile i32, ptr addrspace(4) poison
%two = load volatile i32, ptr addrspace(4) poison
%three = load volatile i32, ptr addrspace(4) poison
%four = load volatile i32, ptr addrspace(4) poison
%five = load volatile i32, ptr addrspace(4) poison
%six = load volatile i32, ptr addrspace(4) poison
%seven = load volatile i32, ptr addrspace(4) poison
%eight = load volatile i32, ptr addrspace(4) poison
%nine = load volatile i32, ptr addrspace(4) poison
%ten = load volatile i32, ptr addrspace(4) poison
%eleven = load volatile i32, ptr addrspace(4) poison
call void asm sideeffect "", "s,s,s,s,s,s,s,s,s,s"(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight, i32 %nine, i32 %ten)
store volatile i32 %one, ptr addrspace(1) poison
store volatile i32 %two, ptr addrspace(1) poison
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -959,7 +959,7 @@ bb0:
br i1 %cmp0, label %bb2, label %bb1

bb1:
%val = load volatile i32, ptr addrspace(4) undef
%val = load volatile i32, ptr addrspace(4) poison
%cmp1 = icmp eq i32 %val, 3
br i1 %cmp1, label %bb3, label %bb2

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
; CHECK: GLOBAL_STORE_DWORDX4
define protected amdgpu_kernel void @test1() local_unnamed_addr !kernel_arg_addr_space !0 !kernel_arg_access_qual !1 !kernel_arg_type !2 !kernel_arg_base_type !2 !kernel_arg_type_qual !3 !kernel_arg_name !4 {
entry:
%tmp = load <3 x i64>, ptr addrspace(4) undef, align 16, !invariant.load !5
%tmp = load <3 x i64>, ptr addrspace(4) poison, align 16, !invariant.load !5
%srcA.load2 = extractelement <3 x i64> %tmp, i32 0
%tmp1 = inttoptr i64 %srcA.load2 to ptr addrspace(1)
%tmp2 = getelementptr inbounds double, ptr addrspace(1) %tmp1, i64 undef
Expand All @@ -36,7 +36,7 @@ entry:
; CHECK: GLOBAL_STORE_DWORDX2
define protected amdgpu_kernel void @test2() local_unnamed_addr !kernel_arg_addr_space !0 !kernel_arg_access_qual !1 !kernel_arg_type !2 !kernel_arg_base_type !2 !kernel_arg_type_qual !3 !kernel_arg_name !4 {
entry:
%tmp = load <3 x i64>, ptr addrspace(4) undef, align 16, !invariant.load !5
%tmp = load <3 x i64>, ptr addrspace(4) poison, align 16, !invariant.load !5
%srcA.load2 = extractelement <3 x i64> %tmp, i32 0
%tmp1 = inttoptr i64 %srcA.load2 to ptr addrspace(1)
%tmp2 = getelementptr inbounds double, ptr addrspace(1) %tmp1, i64 undef
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/call-argument-types.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3959,7 +3959,7 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
; HSA-NEXT: s_mov_b32 s32, 0
; HSA-NEXT: s_swappc_b64 s[30:31], s[8:9]
; HSA-NEXT: s_endpgm
%ptr = load ptr addrspace(1), ptr addrspace(4) undef
%ptr = load ptr addrspace(1), ptr addrspace(4) poison
%val = load <8 x i32>, ptr addrspace(1) %ptr
call void @external_void_func_v8i32(<8 x i32> %val)
ret void
Expand Down Expand Up @@ -4204,7 +4204,7 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; HSA-NEXT: s_mov_b32 s32, 0
; HSA-NEXT: s_swappc_b64 s[30:31], s[8:9]
; HSA-NEXT: s_endpgm
%ptr = load ptr addrspace(1), ptr addrspace(4) undef
%ptr = load ptr addrspace(1), ptr addrspace(4) poison
%val = load <16 x i32>, ptr addrspace(1) %ptr
call void @external_void_func_v16i32(<16 x i32> %val)
ret void
Expand Down Expand Up @@ -4360,7 +4360,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; HSA-NEXT: buffer_store_dword v31, off, s[0:3], s32
; HSA-NEXT: s_swappc_b64 s[30:31], s[12:13]
; HSA-NEXT: s_endpgm
%ptr = load ptr addrspace(1), ptr addrspace(4) undef
%ptr = load ptr addrspace(1), ptr addrspace(4) poison
%val = load <32 x i32>, ptr addrspace(1) %ptr
call void @external_void_func_v32i32(<32 x i32> %val)
ret void
Expand Down Expand Up @@ -4532,7 +4532,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; HSA-NEXT: buffer_store_dword v31, off, s[0:3], s32
; HSA-NEXT: s_swappc_b64 s[30:31], s[8:9]
; HSA-NEXT: s_endpgm
%ptr0 = load ptr addrspace(1), ptr addrspace(4) undef
%ptr0 = load ptr addrspace(1), ptr addrspace(4) poison
%val0 = load <32 x i32>, ptr addrspace(1) %ptr0
%val1 = load i32, ptr addrspace(1) poison
call void @external_void_func_v32i32_i32(<32 x i32> %val0, i32 %val1)
Expand Down Expand Up @@ -4763,7 +4763,7 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; HSA-NEXT: s_mov_b32 s32, 0
; HSA-NEXT: s_swappc_b64 s[30:31], s[8:9]
; HSA-NEXT: s_endpgm
%ptr0 = load ptr addrspace(1), ptr addrspace(4) undef
%ptr0 = load ptr addrspace(1), ptr addrspace(4) poison
%val = load { i8, i32 }, ptr addrspace(1) %ptr0
call void @external_void_func_struct_i8_i32({ i8, i32 } %val)
ret void
Expand Down Expand Up @@ -5300,7 +5300,7 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; HSA-NEXT: v_mov_b32_e32 v3, v18
; HSA-NEXT: s_swappc_b64 s[30:31], s[8:9]
; HSA-NEXT: s_endpgm
%ptr = load ptr addrspace(1), ptr addrspace(4) undef
%ptr = load ptr addrspace(1), ptr addrspace(4) poison
%val = load <16 x i8>, ptr addrspace(1) %ptr
call void @external_void_func_v16i8(<16 x i8> %val)
ret void
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,8 @@ body: |

%3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440
Expand Down Expand Up @@ -105,8 +105,8 @@ body: |

%3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440
Expand Down Expand Up @@ -168,8 +168,8 @@ body: |

%3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440
Expand Down Expand Up @@ -233,8 +233,8 @@ body: |

%3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440
Expand Down Expand Up @@ -310,8 +310,8 @@ body: |

%3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440
Expand Down Expand Up @@ -375,8 +375,8 @@ body: |

%3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -724,7 +724,7 @@ body: |

%2:vgpr_32 = COPY $vgpr0
%0:sgpr_64 = COPY $sgpr0_sgpr1
%3:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`, addrspace 4)
%3:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`, addrspace 4)
%15:vgpr_32 = V_ASHRREV_I32_e64 31, %2, implicit $exec
%16:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %15, %subreg.sub1
%17:vreg_64 = V_LSHLREV_B64_e64 2, killed %16, implicit $exec
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -55,8 +55,8 @@ body: |

%1 = COPY $sgpr4_sgpr5
%0 = COPY $vgpr0
%3 = S_LOAD_DWORDX2_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%4 = S_LOAD_DWORDX2_IMM %1, 8, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
%3 = S_LOAD_DWORDX2_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%4 = S_LOAD_DWORDX2_IMM %1, 8, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)
%7 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%2 = V_MOV_B32_e32 0, implicit $exec
undef %12.sub0 = V_ADD_CO_U32_e32 %4.sub0, %7, implicit-def $vcc, implicit $exec
Expand Down
Loading
Loading