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AMDGPU: Use generated checks in test missing checks #131110

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Mar 14, 2025
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AMDGPU: Use generated checks in test missing checks #131110

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68 changes: 65 additions & 3 deletions llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
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Original file line number Diff line number Diff line change
@@ -1,10 +1,72 @@
; RUN: llc < %s
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
target triple = "amdgcn-amd-amdhsa"
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s

@_RSENC_gDcd_______________________________ = external protected addrspace(1) externally_initialized global [4096 x i8], align 16

define protected amdgpu_kernel void @_RSENC_PRInit__________________________________(i1 %c0) local_unnamed_addr #0 {
; CHECK-LABEL: _RSENC_PRInit__________________________________:
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what the heck of the function name is...

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Came from something real I assume, but I have no idea

; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; CHECK-NEXT: flat_load_dword v0, v[0:1]
; CHECK-NEXT: s_add_u32 s0, s0, s17
; CHECK-NEXT: s_mov_b32 s4, 0xf19b3
; CHECK-NEXT: s_addc_u32 s1, s1, 0
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshl_add_u32 v0, v0, 1, v0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz .LBB0_12
; CHECK-NEXT: ; %bb.1: ; %if.end15
; CHECK-NEXT: s_load_dword s4, s[8:9], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_bitcmp1_b32 s4, 0
; CHECK-NEXT: s_cselect_b64 s[4:5], -1, 0
; CHECK-NEXT: s_and_b64 vcc, exec, s[4:5]
; CHECK-NEXT: s_cbranch_vccnz .LBB0_12
; CHECK-NEXT: .LBB0_2: ; %while.cond.i
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
; CHECK-NEXT: ; %bb.3: ; %if.end60
; CHECK-NEXT: s_mov_b64 vcc, exec
; CHECK-NEXT: s_cbranch_execz .LBB0_11
; CHECK-NEXT: ; %bb.4: ; %if.end5.i
; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccz .LBB0_11
; CHECK-NEXT: ; %bb.5: ; %if.end5.i314
; CHECK-NEXT: s_mov_b64 vcc, exec
; CHECK-NEXT: s_cbranch_execz .LBB0_11
; CHECK-NEXT: ; %bb.6: ; %if.end5.i338
; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccz .LBB0_11
; CHECK-NEXT: ; %bb.7: ; %if.end5.i362
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _RSENC_gDcd_______________________________@rel32@lo+1157
; CHECK-NEXT: s_addc_u32 s5, s5, _RSENC_gDcd_______________________________@rel32@hi+1165
; CHECK-NEXT: global_load_ubyte v1, v0, s[4:5]
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: buffer_store_byte v0, v0, s[0:3], 0 offen
; CHECK-NEXT: s_waitcnt vmcnt(1)
; CHECK-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:257
; CHECK-NEXT: s_cbranch_execz .LBB0_11
; CHECK-NEXT: ; %bb.8: ; %if.end5.i400
; CHECK-NEXT: flat_load_ubyte v0, v[0:1]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
; CHECK-NEXT: s_and_b64 exec, exec, vcc
; CHECK-NEXT: s_cbranch_execz .LBB0_11
; CHECK-NEXT: ; %bb.9: ; %if.then404
; CHECK-NEXT: s_movk_i32 s4, 0x1000
; CHECK-NEXT: .LBB0_10: ; %for.body564
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_sub_i32 s4, s4, 32
; CHECK-NEXT: s_cmp_lg_u32 s4, 0
; CHECK-NEXT: s_cbranch_scc1 .LBB0_10
; CHECK-NEXT: .LBB0_11: ; %UnifiedUnreachableBlock
; CHECK-NEXT: ; divergent unreachable
; CHECK-NEXT: .LBB0_12: ; %UnifiedReturnBlock
; CHECK-NEXT: s_endpgm
entry:
%runtimeVersionCopy = alloca [128 x i8], align 16, addrspace(5)
%licenseVersionCopy = alloca [128 x i8], align 16, addrspace(5)
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