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[RISCV] Set AllocationPriority in line with LMUL #131176

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Merged
merged 3 commits into from
Mar 18, 2025
Merged

[RISCV] Set AllocationPriority in line with LMUL #131176

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39fd13e
[RISCV] Set AllocationPriority in line with LMUL
preames Mar 13, 2025
6cf0b43
Address review comment
preames Mar 13, 2025
def2991
Merge branch 'main' into pr-riscv-allocation-priority
preames Mar 18, 2025
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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Expand Up @@ -720,6 +720,8 @@ class VReg<list<ValueType> regTypes, dag regList, int Vlmul, int nf = 1>

let Size = !mul(VLMul, NF, 64);
let CopyCost = !mul(VLMul, NF);
// Prefer to allocate high LMUL registers first.
let AllocationPriority = !if(!gt(Vlmul, 1), Vlmul, 0);
}

defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
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Expand Up @@ -20,10 +20,10 @@ define signext i32 @sum(ptr %a, i32 signext %n, i1 %prof.min.iters.check, <vscal
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_4: # %vector.ph
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; CHECK-NEXT: vredsum.vs v8, v12, v8, v0.t
; CHECK-NEXT: vredsum.vs v8, v8, v12, v0.t
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
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Expand Up @@ -106,12 +106,12 @@ define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) {
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsext.vf8 v16, v8
; CHECK-NEXT: vsaddu.vx v8, v16, a1
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v16
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2
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40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
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Expand Up @@ -9,21 +9,21 @@ define void @test(ptr %ref_array, ptr %sad_array) {
; RV32: # %bb.0: # %entry
; RV32-NEXT: th.lwd a2, a3, (a0), 0, 3
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vle8.v v8, (a2)
; RV32-NEXT: vle8.v v12, (a2)
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vzext.vf4 v12, v8
; RV32-NEXT: vmv.s.x v8, zero
; RV32-NEXT: vredsum.vs v9, v12, v8
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: vzext.vf4 v8, v12
; RV32-NEXT: vmv.s.x v12, zero
; RV32-NEXT: vredsum.vs v8, v8, v12
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: th.swia a0, (a1), 4, 0
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vle8.v v9, (a3)
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vle8.v v13, (a3)
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vi v9, v10, 4
; RV32-NEXT: vslideup.vi v13, v8, 4
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vzext.vf4 v12, v9
; RV32-NEXT: vredsum.vs v8, v12, v8
; RV32-NEXT: vzext.vf4 v8, v13
; RV32-NEXT: vredsum.vs v8, v8, v12
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: ret
Expand All @@ -32,21 +32,21 @@ define void @test(ptr %ref_array, ptr %sad_array) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: th.ldd a2, a3, (a0), 0, 4
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV64-NEXT: vle8.v v8, (a2)
; RV64-NEXT: vle8.v v12, (a2)
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vzext.vf4 v12, v8
; RV64-NEXT: vmv.s.x v8, zero
; RV64-NEXT: vredsum.vs v9, v12, v8
; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: vzext.vf4 v8, v12
; RV64-NEXT: vmv.s.x v12, zero
; RV64-NEXT: vredsum.vs v8, v8, v12
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: th.swia a0, (a1), 4, 0
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV64-NEXT: vle8.v v9, (a3)
; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vle8.v v13, (a3)
; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vslideup.vi v9, v10, 4
; RV64-NEXT: vslideup.vi v13, v8, 4
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vzext.vf4 v12, v9
; RV64-NEXT: vredsum.vs v8, v12, v8
; RV64-NEXT: vzext.vf4 v8, v13
; RV64-NEXT: vredsum.vs v8, v8, v12
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: ret
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7 changes: 4 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
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Expand Up @@ -8,10 +8,11 @@ define dso_local <16 x i16> @interleave(<8 x i16> %v0, <8 x i16> %v1) {
; CHECK-LABEL: interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v11, v8
; CHECK-NEXT: vwaddu.vv v8, v11, v10
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
entry:
%v2 = shufflevector <8 x i16> %v0, <8 x i16> poison, <16 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef>
Expand Down
50 changes: 25 additions & 25 deletions llvm/test/CodeGen/RISCV/rvv/compressstore.ll
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Expand Up @@ -200,12 +200,12 @@ define void @test_compresstore_v256i8(ptr %p, <256 x i1> %mask, <256 x i8> %data
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vmv1r.v v7, v8
; RV64-NEXT: li a2, 128
; RV64-NEXT: vslidedown.vi v9, v0, 1
; RV64-NEXT: vslidedown.vi v8, v0, 1
; RV64-NEXT: vmv.x.s a3, v0
; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; RV64-NEXT: vle8.v v24, (a1)
; RV64-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV64-NEXT: vmv.x.s a1, v9
; RV64-NEXT: vmv.x.s a1, v8
; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; RV64-NEXT: vcompress.vm v8, v16, v0
; RV64-NEXT: vcpop.m a4, v0
Expand All @@ -227,14 +227,14 @@ define void @test_compresstore_v256i8(ptr %p, <256 x i1> %mask, <256 x i8> %data
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv1r.v v7, v8
; RV32-NEXT: li a2, 128
; RV32-NEXT: vslidedown.vi v9, v0, 1
; RV32-NEXT: vslidedown.vi v8, v0, 1
; RV32-NEXT: li a3, 32
; RV32-NEXT: vmv.x.s a4, v0
; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; RV32-NEXT: vle8.v v24, (a1)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v6, v9, a3
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vsrl.vx v6, v8, a3
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: vsrl.vx v5, v0, a3
; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; RV32-NEXT: vcompress.vm v8, v16, v0
Expand Down Expand Up @@ -438,16 +438,16 @@ define void @test_compresstore_v128i16(ptr %p, <128 x i1> %mask, <128 x i16> %da
; RV64-NEXT: vcompress.vm v24, v8, v0
; RV64-NEXT: vcpop.m a2, v0
; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v0, 8
; RV64-NEXT: vslidedown.vi v7, v0, 8
; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; RV64-NEXT: vcompress.vm v0, v16, v8
; RV64-NEXT: vcpop.m a1, v8
; RV64-NEXT: vcompress.vm v8, v16, v7
; RV64-NEXT: vcpop.m a1, v7
; RV64-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; RV64-NEXT: vse16.v v24, (a0)
; RV64-NEXT: slli a2, a2, 1
; RV64-NEXT: add a0, a0, a2
; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; RV64-NEXT: vse16.v v0, (a0)
; RV64-NEXT: vse16.v v8, (a0)
; RV64-NEXT: ret
;
; RV32-LABEL: test_compresstore_v128i16:
Expand Down Expand Up @@ -635,16 +635,16 @@ define void @test_compresstore_v64i32(ptr %p, <64 x i1> %mask, <64 x i32> %data)
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV64-NEXT: vse32.v v24, (a0)
; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v0, 4
; RV64-NEXT: vslidedown.vi v24, v0, 4
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-NEXT: vmv.x.s a1, v0
; RV64-NEXT: vcompress.vm v24, v16, v8
; RV64-NEXT: vcpop.m a2, v8
; RV64-NEXT: vcompress.vm v8, v16, v24
; RV64-NEXT: vcpop.m a2, v24
; RV64-NEXT: cpopw a1, a1
; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV64-NEXT: vse32.v v24, (a0)
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
;
; RV32-LABEL: test_compresstore_v64i32:
Expand All @@ -654,16 +654,16 @@ define void @test_compresstore_v64i32(ptr %p, <64 x i1> %mask, <64 x i32> %data)
; RV32-NEXT: vcompress.vm v24, v8, v0
; RV32-NEXT: vcpop.m a2, v0
; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v8, v0, 4
; RV32-NEXT: vslidedown.vi v7, v0, 4
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vcompress.vm v0, v16, v8
; RV32-NEXT: vcpop.m a1, v8
; RV32-NEXT: vcompress.vm v8, v16, v7
; RV32-NEXT: vcpop.m a1, v7
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vse32.v v24, (a0)
; RV32-NEXT: slli a2, a2, 2
; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vse32.v v0, (a0)
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
entry:
tail call void @llvm.masked.compressstore.v64i32(<64 x i32> %data, ptr align 4 %p, <64 x i1> %mask)
Expand Down Expand Up @@ -796,18 +796,18 @@ define void @test_compresstore_v32i64(ptr %p, <32 x i1> %mask, <32 x i64> %data)
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vse64.v v24, (a0)
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v8, v0, 2
; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; RV64-NEXT: vmv.x.s a1, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vcompress.vm v24, v16, v8
; RV64-NEXT: vcompress.vm v8, v16, v24
; RV64-NEXT: zext.h a1, a1
; RV64-NEXT: cpopw a1, a1
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vcpop.m a1, v8
; RV64-NEXT: vcpop.m a1, v24
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vse64.v v24, (a0)
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
;
; RV32-LABEL: test_compresstore_v32i64:
Expand All @@ -818,18 +818,18 @@ define void @test_compresstore_v32i64(ptr %p, <32 x i1> %mask, <32 x i64> %data)
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vse64.v v24, (a0)
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v8, v0, 2
; RV32-NEXT: vslidedown.vi v24, v0, 2
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; RV32-NEXT: vmv.x.s a1, v0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vcompress.vm v24, v16, v8
; RV32-NEXT: vcompress.vm v8, v16, v24
; RV32-NEXT: zext.h a1, a1
; RV32-NEXT: cpop a1, a1
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: vcpop.m a1, v8
; RV32-NEXT: vcpop.m a1, v24
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vse64.v v24, (a0)
; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret
entry:
tail call void @llvm.masked.compressstore.v32i64(<32 x i64> %data, ptr align 8 %p, <32 x i1> %mask)
Expand Down
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