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[AMDGPU][True16][CodeGen] enable true16 for more codegen test patch 3 #131212

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Mar 14, 2025
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[AMDGPU][True16][CodeGen] enable true16 for more codegen test patch 3 #131212

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318 changes: 218 additions & 100 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
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31 changes: 21 additions & 10 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,8 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s

define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %data) {
; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
Expand Down Expand Up @@ -34,15 +35,25 @@ define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %dat
; GFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, off, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED]
; GFX10-PACKED-NEXT: s_endpgm
;
; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: s_clause 0x1
; GFX11-PACKED-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s6
; GFX11-PACKED-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
; GFX11-PACKED-NEXT: s_endpgm
; GFX11-PACKED-TRUE16-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED-TRUE16: ; %bb.0: ; %main_body
; GFX11-PACKED-TRUE16-NEXT: s_clause 0x1
; GFX11-PACKED-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX11-PACKED-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-PACKED-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-TRUE16-NEXT: v_mov_b16_e32 v0.l, s6
; GFX11-PACKED-TRUE16-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
; GFX11-PACKED-TRUE16-NEXT: s_endpgm
;
; GFX11-PACKED-FAKE16-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED-FAKE16: ; %bb.0: ; %main_body
; GFX11-PACKED-FAKE16-NEXT: s_clause 0x1
; GFX11-PACKED-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX11-PACKED-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-PACKED-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-FAKE16-NEXT: v_mov_b32_e32 v0, s6
; GFX11-PACKED-FAKE16-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
; GFX11-PACKED-FAKE16-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %data, ptr addrspace(8) %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void
Expand Down
46 changes: 31 additions & 15 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,10 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED,GFX12-PACKED-TRUE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED,GFX12-PACKED-FAKE16 %s

define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
Expand Down Expand Up @@ -104,19 +106,33 @@ define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) {
; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
; GFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, v1
; GFX11-PACKED-NEXT: ; return to shader part epilog
;
; GFX12-PACKED-LABEL: tbuffer_load_d16_xyz:
; GFX12-PACKED: ; %bb.0: ; %main_body
; GFX12-PACKED-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], null format:[BUF_FMT_32_FLOAT]
; GFX12-PACKED-NEXT: s_wait_loadcnt 0x0
; GFX12-PACKED-NEXT: v_mov_b32_e32 v0, v1
; GFX12-PACKED-NEXT: ; return to shader part epilog
; GFX11-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
; GFX11-PACKED-TRUE16: ; %bb.0: ; %main_body
; GFX11-PACKED-TRUE16-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX11-PACKED-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX11-PACKED-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
; GFX11-PACKED-FAKE16: ; %bb.0: ; %main_body
; GFX11-PACKED-FAKE16-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX11-PACKED-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-FAKE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-PACKED-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
; GFX12-PACKED-TRUE16: ; %bb.0: ; %main_body
; GFX12-PACKED-TRUE16-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], null format:[BUF_FMT_32_FLOAT]
; GFX12-PACKED-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-PACKED-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX12-PACKED-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
; GFX12-PACKED-FAKE16: ; %bb.0: ; %main_body
; GFX12-PACKED-FAKE16-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], null format:[BUF_FMT_32_FLOAT]
; GFX12-PACKED-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-PACKED-FAKE16-NEXT: v_mov_b32_e32 v0, v1
; GFX12-PACKED-FAKE16-NEXT: ; return to shader part epilog
main_body:
%data = call <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <3 x half> %data, i32 2
Expand Down
78 changes: 57 additions & 21 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,12 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG %s
; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-TRUE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-FAKE16 %s
; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-TRUE16 %s
; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-FAKE16 %s

define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data) {
; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
Expand Down Expand Up @@ -36,25 +39,55 @@ define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data) {
; GFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, off, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED]
; GFX10-PACKED-NEXT: s_endpgm
;
; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: s_clause 0x1
; GFX11-PACKED-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s6
; GFX11-PACKED-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
; GFX11-PACKED-NEXT: s_endpgm
; GFX11-PACKED-TRUE16-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED-TRUE16: ; %bb.0: ; %main_body
; GFX11-PACKED-TRUE16-NEXT: s_clause 0x1
; GFX11-PACKED-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX11-PACKED-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-PACKED-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-TRUE16-NEXT: v_mov_b16_e32 v0.l, s6
; GFX11-PACKED-TRUE16-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
; GFX11-PACKED-TRUE16-NEXT: s_endpgm
;
; GFX12-PACKED-LABEL: tbuffer_store_d16_x:
; GFX12-PACKED: ; %bb.0: ; %main_body
; GFX12-PACKED-NEXT: s_clause 0x1
; GFX12-PACKED-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-PACKED-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-PACKED-NEXT: s_wait_kmcnt 0x0
; GFX12-PACKED-NEXT: v_mov_b32_e32 v0, s6
; GFX12-PACKED-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
; GFX12-PACKED-NEXT: s_endpgm
; GFX11-PACKED-FAKE16-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED-FAKE16: ; %bb.0: ; %main_body
; GFX11-PACKED-FAKE16-NEXT: s_clause 0x1
; GFX11-PACKED-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX11-PACKED-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-PACKED-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-FAKE16-NEXT: v_mov_b32_e32 v0, s6
; GFX11-PACKED-FAKE16-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
; GFX11-PACKED-FAKE16-NEXT: s_endpgm
;
; GFX12-PACKED-SDAG-TRUE16-LABEL: tbuffer_store_d16_x:
; GFX12-PACKED-SDAG-TRUE16: ; %bb.0: ; %main_body
; GFX12-PACKED-SDAG-TRUE16-NEXT: s_clause 0x1
; GFX12-PACKED-SDAG-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-PACKED-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-PACKED-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-PACKED-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, s6
; GFX12-PACKED-SDAG-TRUE16-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
; GFX12-PACKED-SDAG-TRUE16-NEXT: s_endpgm
;
; GFX12-PACKED-SDAG-FAKE16-LABEL: tbuffer_store_d16_x:
; GFX12-PACKED-SDAG-FAKE16: ; %bb.0: ; %main_body
; GFX12-PACKED-SDAG-FAKE16-NEXT: s_clause 0x1
; GFX12-PACKED-SDAG-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-PACKED-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-PACKED-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-PACKED-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, s6
; GFX12-PACKED-SDAG-FAKE16-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
; GFX12-PACKED-SDAG-FAKE16-NEXT: s_endpgm
;
; GFX12-PACKED-GISEL-LABEL: tbuffer_store_d16_x:
; GFX12-PACKED-GISEL: ; %bb.0: ; %main_body
; GFX12-PACKED-GISEL-NEXT: s_clause 0x1
; GFX12-PACKED-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-PACKED-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-PACKED-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX12-PACKED-GISEL-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
; GFX12-PACKED-GISEL-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void
Expand Down Expand Up @@ -264,3 +297,6 @@ declare void @llvm.amdgcn.raw.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32,
declare void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32)
declare void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32)
declare void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX12-PACKED-GISEL-FAKE16: {{.*}}
; GFX12-PACKED-GISEL-TRUE16: {{.*}}
25 changes: 17 additions & 8 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,8 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s

define amdgpu_ps half @tbuffer_load_d16_x(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
Expand Down Expand Up @@ -101,13 +102,21 @@ define amdgpu_ps half @tbuffer_load_d16_xyz(ptr addrspace(8) inreg %rsrc) {
; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
; GFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, 0
; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, v1
; GFX11-PACKED-NEXT: ; return to shader part epilog
; GFX11-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
; GFX11-PACKED-TRUE16: ; %bb.0: ; %main_body
; GFX11-PACKED-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-PACKED-TRUE16-NEXT: tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
; GFX11-PACKED-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX11-PACKED-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
; GFX11-PACKED-FAKE16: ; %bb.0: ; %main_body
; GFX11-PACKED-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-PACKED-FAKE16-NEXT: tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
; GFX11-PACKED-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-FAKE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-PACKED-FAKE16-NEXT: ; return to shader part epilog
main_body:
%data = call <3 x half> @llvm.amdgcn.struct.ptr.tbuffer.load.v3f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <3 x half> %data, i32 2
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34 changes: 23 additions & 11 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,8 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s

define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %data, i32 %vindex) {
; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
Expand Down Expand Up @@ -37,16 +38,27 @@ define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %dat
; GFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
; GFX10-PACKED-NEXT: s_endpgm
;
; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: s_clause 0x1
; GFX11-PACKED-NEXT: s_load_b64 s[6:7], s[4:5], 0x10
; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s6
; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s7
; GFX11-PACKED-NEXT: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX11-PACKED-NEXT: s_endpgm
; GFX11-PACKED-TRUE16-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED-TRUE16: ; %bb.0: ; %main_body
; GFX11-PACKED-TRUE16-NEXT: s_clause 0x1
; GFX11-PACKED-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x10
; GFX11-PACKED-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-PACKED-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-TRUE16-NEXT: v_mov_b16_e32 v0.l, s6
; GFX11-PACKED-TRUE16-NEXT: v_mov_b32_e32 v1, s7
; GFX11-PACKED-TRUE16-NEXT: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX11-PACKED-TRUE16-NEXT: s_endpgm
;
; GFX11-PACKED-FAKE16-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED-FAKE16: ; %bb.0: ; %main_body
; GFX11-PACKED-FAKE16-NEXT: s_clause 0x1
; GFX11-PACKED-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x10
; GFX11-PACKED-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-PACKED-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-FAKE16-NEXT: v_mov_b32_e32 v0, s6
; GFX11-PACKED-FAKE16-NEXT: v_mov_b32_e32 v1, s7
; GFX11-PACKED-FAKE16-NEXT: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX11-PACKED-FAKE16-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.tbuffer.store.f16(half %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
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