Skip to content

[AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32 #131306

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Mar 17, 2025
Merged

[AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32 #131306

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
734fb1f
[AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32
Pierre-vh Mar 5, 2025
7559408
remove comment
Pierre-vh Mar 17, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
26 changes: 24 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2416,9 +2416,10 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
Register DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);

if (DstTy.getSizeInBits() == 1) {
const RegisterBank *DstBank =
const RegisterBank *DstBank =
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;

if (DstTy.getSizeInBits() == 1) {
if (DstBank == &AMDGPU::VCCRegBank)
break;

Expand All @@ -2432,6 +2433,27 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
return;
}

if (DstTy.getSizeInBits() == 16 && DstBank == &AMDGPU::SGPRRegBank) {
const LLT S32 = LLT::scalar(32);
MachineBasicBlock *MBB = MI.getParent();
MachineFunction *MF = MBB->getParent();
ApplyRegBankMapping ApplySALU(B, *this, MRI, &AMDGPU::SGPRRegBank);
LegalizerHelper Helper(*MF, ApplySALU, B);
// Widen to S32, but handle `G_XOR x, -1` differently. Legalizer widening
// will use a G_ANYEXT to extend the -1 which prevents matching G_XOR -1
// as "not".
Comment on lines +2442 to +2444
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Maybe the legalizerhelper should account for this and sext -1s

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

s_not_b32 s1, s3 has no advantage over s_xor_b32 s1, s3, -1 so maybe it's not worth worrying about?

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'd still expect to form not patterns canonically. I don't know why the iSA provides it, but other patterns to make use of not

if (MI.getOpcode() == AMDGPU::G_XOR &&
mi_match(MI.getOperand(2).getReg(), MRI, m_SpecificICstOrSplat(-1))) {
Helper.widenScalarSrc(MI, S32, 1, AMDGPU::G_ANYEXT);
Helper.widenScalarSrc(MI, S32, 2, AMDGPU::G_SEXT);
Helper.widenScalarDst(MI, S32);
} else {
if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
llvm_unreachable("widen scalar should have succeeded");
}
return;
}

if (DstTy.getSizeInBits() != 64)
break;

Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -391,20 +391,20 @@ define amdgpu_ps i16 @s_andn2_i16_commute(i16 inreg %src0, i16 inreg %src1) {
define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) {
; GCN-LABEL: s_andn2_i16_multi_use:
; GCN: ; %bb.0:
; GCN-NEXT: s_xor_b32 s1, s3, -1
; GCN-NEXT: s_not_b32 s1, s3
; GCN-NEXT: s_andn2_b32 s0, s2, s3
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_andn2_i16_multi_use:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_andn2_b32 s0, s2, s3
; GFX10-NEXT: s_xor_b32 s1, s3, -1
; GFX10-NEXT: s_not_b32 s1, s3
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_andn2_i16_multi_use:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_not1_b32 s0, s2, s3
; GFX11-NEXT: s_xor_b32 s1, s3, -1
; GFX11-NEXT: s_not_b32 s1, s3
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1
%and = and i16 %src0, %not.src1
Expand Down Expand Up @@ -482,14 +482,14 @@ define amdgpu_ps float @v_andn2_i16_sv(i16 inreg %src0, i16 %src1) {
define amdgpu_ps float @v_andn2_i16_vs(i16 %src0, i16 inreg %src1) {
; GCN-LABEL: v_andn2_i16_vs:
; GCN: ; %bb.0:
; GCN-NEXT: s_xor_b32 s0, s2, -1
; GCN-NEXT: s_not_b32 s0, s2
; GCN-NEXT: v_and_b32_e32 v0, s0, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: v_andn2_i16_vs:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_xor_b32 s0, s2, -1
; GFX10PLUS-NEXT: s_not_b32 s0, s2
; GFX10PLUS-NEXT: v_and_b32_e32 v0, s0, v0
; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10PLUS-NEXT: ; return to shader part epilog
Expand Down
Loading
Loading