[NFC][AMDGPU] Replace direct arch comparison with isAMDGCN()

llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp

@@ -96,8 +96,7 @@ static bool alwaysInlineImpl(Module &M, bool GlobalOpt) {
 
   for (GlobalAlias &A : M.aliases()) {
     if (Function* F = dyn_cast<Function>(A.getAliasee())) {
-      if (TT.getArch() == Triple::amdgcn &&
-          A.getLinkage() != GlobalValue::InternalLinkage)
+      if (TT.isAMDGCN() && A.getLinkage() != GlobalValue::InternalLinkage)
         continue;
       Changed = true;
       A.replaceAllUsesWith(F);

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

@@ -3867,7 +3867,7 @@ SDValue AMDGPUDAGToDAGISel::getHi16Elt(SDValue In) const {
 }
 
 bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
-  assert(CurDAG->getTarget().getTargetTriple().getArch() == Triple::amdgcn);
+  assert(CurDAG->getTarget().getTargetTriple().isAMDGCN());
 
   const SIRegisterInfo *SIRI =
     static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());

llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

@@ -133,7 +133,7 @@ class AMDGPUPromoteAllocaImpl {
   AMDGPUPromoteAllocaImpl(TargetMachine &TM, LoopInfo &LI) : TM(TM), LI(LI) {
 
     const Triple &TT = TM.getTargetTriple();
-    IsAMDGCN = TT.getArch() == Triple::amdgcn;
+    IsAMDGCN = TT.isAMDGCN();
     IsAMDHSA = TT.getOS() == Triple::AMDHSA;
   }
 

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

@@ -389,13 +389,13 @@ AMDGPUDwarfFlavour AMDGPUSubtarget::getAMDGPUDwarfFlavour() const {
 }
 
 const AMDGPUSubtarget &AMDGPUSubtarget::get(const MachineFunction &MF) {
-  if (MF.getTarget().getTargetTriple().getArch() == Triple::amdgcn)
+  if (MF.getTarget().getTargetTriple().isAMDGCN())
     return static_cast<const AMDGPUSubtarget&>(MF.getSubtarget<GCNSubtarget>());
   return static_cast<const AMDGPUSubtarget &>(MF.getSubtarget<R600Subtarget>());
 }
 
 const AMDGPUSubtarget &AMDGPUSubtarget::get(const TargetMachine &TM, const Function &F) {
-  if (TM.getTargetTriple().getArch() == Triple::amdgcn)
+  if (TM.getTargetTriple().isAMDGCN())
     return static_cast<const AMDGPUSubtarget&>(TM.getSubtarget<GCNSubtarget>(F));
   return static_cast<const AMDGPUSubtarget &>(
       TM.getSubtarget<R600Subtarget>(F));

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

@@ -161,9 +161,7 @@ class AMDGPUSubtarget {
     return isAmdHsaOS() || isMesaKernel(F);
   }
 
-  bool isGCN() const {
-    return TargetTriple.getArch() == Triple::amdgcn;
-  }
+  bool isGCN() const { return TargetTriple.isAMDGCN(); }
 
   bool isGCN3Encoding() const {
     return GCN3Encoding;

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -690,7 +690,7 @@ static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
     return GPU;
 
   // Need to default to a target with flat support for HSA.
-  if (TT.getArch() == Triple::amdgcn)
+  if (TT.isAMDGCN())
     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
 
   return "r600";
@@ -714,7 +714,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
           getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
       TLOF(createTLOF(getTargetTriple())) {
   initAsmInfo();
-  if (TT.getArch() == Triple::amdgcn) {
+  if (TT.isAMDGCN()) {
     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
@@ -1198,8 +1198,7 @@ void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
 void AMDGPUPassConfig::addIRPasses() {
   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
 
-  Triple::ArchType Arch = TM.getTargetTriple().getArch();
-  if (RemoveIncompatibleFunctions && Arch == Triple::amdgcn)
+  if (RemoveIncompatibleFunctions && TM.getTargetTriple().isAMDGCN())
     addPass(createAMDGPURemoveIncompatibleFunctionsPass(&TM));
 
   // There is no reason to run these.
@@ -1223,7 +1222,7 @@ void AMDGPUPassConfig::addIRPasses() {
   addPass(createAlwaysInlinerLegacyPass());
 
   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
-  if (Arch == Triple::r600)
+  if (TM.getTargetTriple().getArch() == Triple::r600)
     addPass(createR600OpenCLImageTypeLoweringPass());
 
   // Make enqueued block runtime handles externally visible.
@@ -1242,7 +1241,7 @@ void AMDGPUPassConfig::addIRPasses() {
     addPass(createInferAddressSpacesPass());
 
   // Run atomic optimizer before Atomic Expand
-  if ((TM.getTargetTriple().getArch() == Triple::amdgcn) &&
+  if ((TM.getTargetTriple().isAMDGCN()) &&
       (TM.getOptLevel() >= CodeGenOptLevel::Less) &&
       (AMDGPUAtomicOptimizerStrategy != ScanOptions::None)) {
     addPass(createAMDGPUAtomicOptimizerPass(AMDGPUAtomicOptimizerStrategy));
@@ -1265,7 +1264,7 @@ void AMDGPUPassConfig::addIRPasses() {
         }));
     }
 
-    if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
+    if (TM.getTargetTriple().isAMDGCN()) {
       // TODO: May want to move later or split into an early and late one.
       addPass(createAMDGPUCodeGenPreparePass());
     }
@@ -1295,17 +1294,16 @@ void AMDGPUPassConfig::addIRPasses() {
 }
 
 void AMDGPUPassConfig::addCodeGenPrepare() {
-  if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
+  if (TM->getTargetTriple().isAMDGCN()) {
     // FIXME: This pass adds 2 hacky attributes that can be replaced with an
     // analysis, and should be removed.
     addPass(createAMDGPUAnnotateKernelFeaturesPass());
   }
 
-  if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
-      EnableLowerKernelArguments)
+  if (TM->getTargetTriple().isAMDGCN() && EnableLowerKernelArguments)
     addPass(createAMDGPULowerKernelArgumentsPass());
 
-  if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
+  if (TM->getTargetTriple().isAMDGCN()) {
     // This lowering has been placed after codegenprepare to take advantage of
     // address mode matching (which is why it isn't put with the LDS lowerings).
     // It could be placed anywhere before uniformity annotations (an analysis

llvm/lib/Target/AMDGPU/GCNSubtarget.cpp

@@ -137,7 +137,7 @@ GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
   if (LDSBankCount == 0)
     LDSBankCount = 32;
 
-  if (TT.getArch() == Triple::amdgcn && AddressableLocalMemorySize == 0)
+  if (TT.isAMDGCN() && AddressableLocalMemorySize == 0)
     AddressableLocalMemorySize = 32768;
 
   LocalMemorySize = AddressableLocalMemorySize;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

@@ -238,7 +238,7 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
 
 public:
   ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)
-      : AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
+      : AMDGPUAsmBackend(T), Is64Bit(TT.isAMDGCN()),
         HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
     switch (TT.getOS()) {
     case Triple::AMDHSA:

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp

@@ -28,15 +28,15 @@ const MCAsmInfo::VariantKindDesc variantKindDescs[] = {
 
 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
                                  const MCTargetOptions &Options) {
-  CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4;
+  CodePointerSize = (TT.isAMDGCN()) ? 8 : 4;
   StackGrowsUp = true;
   HasSingleParameterDotFile = false;
   //===------------------------------------------------------------------===//
   MinInstAlignment = 4;
 
   // This is the maximum instruction encoded size for gfx10. With a known
   // subtarget, it can be reduced to 8 bytes.
-  MaxInstLength = (TT.getArch() == Triple::amdgcn) ? 20 : 16;
+  MaxInstLength = (TT.isAMDGCN()) ? 20 : 16;
   SeparatorString = "\n";
   CommentString = ";";
   InlineAsmStart = ";#ASMSTART";

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

@@ -712,7 +712,7 @@ unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
 }
 
 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
-  assert(STI.getTargetTriple().getArch() == Triple::amdgcn);
+  assert(STI.getTargetTriple().isAMDGCN());
 
   switch (STI.getTargetTriple().getOS()) {
   default: