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[RISCV] Add statistics for total LMUL spilled/reloaded #131747

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Merged
merged 2 commits into from
Mar 19, 2025
Merged

[RISCV] Add statistics for total LMUL spilled/reloaded #131747

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e545a3d
[RISCV] Add statistics for total LMUL spilled/reloaded
lukel97 Mar 18, 2025
fa445ec
Reword in terms of vector registers
lukel97 Mar 18, 2025
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9 changes: 9 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#include "RISCVSubtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervals.h"
Expand All @@ -43,6 +44,12 @@ using namespace llvm;
#define GET_INSTRINFO_NAMED_OPS
#include "RISCVGenInstrInfo.inc"

#define DEBUG_TYPE "riscv-instr-info"
STATISTIC(NumVRegSpilled,
"Number of registers within vector register groups spilled");
STATISTIC(NumVRegReloaded,
"Number of registers within vector register groups reloaded");

static cl::opt<bool> PreferWholeRegisterMove(
"riscv-prefer-whole-register-move", cl::init(false), cl::Hidden,
cl::desc("Prefer whole register move for vector registers."));
Expand Down Expand Up @@ -657,6 +664,7 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addFrameIndex(FI)
.addMemOperand(MMO)
.setMIFlag(Flags);
NumVRegSpilled += TRI->getRegSizeInBits(*RC) / RISCV::RVVBitsPerBlock;
} else {
MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
Expand Down Expand Up @@ -747,6 +755,7 @@ void RISCVInstrInfo::loadRegFromStackSlot(
.addFrameIndex(FI)
.addMemOperand(MMO)
.setMIFlag(Flags);
NumVRegReloaded += TRI->getRegSizeInBits(*RC) / RISCV::RVVBitsPerBlock;
} else {
MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
Expand Down