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[LLVM][CodeGen][AArch64] Improve PTEST removal by looking through copies. #132041

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Merged
merged 2 commits into from
Mar 20, 2025
Merged

[LLVM][CodeGen][AArch64] Improve PTEST removal by looking through copies. #132041

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715d144
Add test.
paulwalker-arm Mar 19, 2025
6d3a477
[LLVM][CodeGen][AArch64] Improve PTEST removal by looking through cop…
paulwalker-arm Mar 18, 2025
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12 changes: 10 additions & 2 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1491,13 +1491,22 @@ AArch64InstrInfo::canRemovePTestInstr(MachineInstr *PTest, MachineInstr *Mask,
if ((Mask == Pred) && PTest->getOpcode() == AArch64::PTEST_PP_ANY)
return PredOpcode;

auto PTestLikeMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());

// If the PTEST like instruction's general predicate is not `Mask`, attempt
// to look through a copy and try again. This is because some instructions
// take a predicate whose register class is a subset of its result class.
if (Mask != PTestLikeMask && PTestLikeMask->isFullCopy() &&
PTestLikeMask->getOperand(1).getReg().isVirtual())
PTestLikeMask =
MRI->getUniqueVRegDef(PTestLikeMask->getOperand(1).getReg());

// For PTEST(PTRUE_ALL, PTEST_LIKE), the PTEST is redundant if the
// the element size matches and either the PTEST_LIKE instruction uses
// the same all active mask or the condition is "any".
if (isPTrueOpcode(MaskOpcode) && Mask->getOperand(1).getImm() == 31 &&
getElementSizeForOpcode(MaskOpcode) ==
getElementSizeForOpcode(PredOpcode)) {
auto PTestLikeMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());
if (Mask == PTestLikeMask || PTest->getOpcode() == AArch64::PTEST_PP_ANY)
return PredOpcode;
}
Expand All @@ -1524,7 +1533,6 @@ AArch64InstrInfo::canRemovePTestInstr(MachineInstr *PTest, MachineInstr *Mask,
// active flag, whereas the PTEST instruction with the same mask doesn't.
// For PTEST_ANY this doesn't apply as the flags in this case would be
// identical regardless of element size.
auto PTestLikeMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());
uint64_t PredElementSize = getElementSizeForOpcode(PredOpcode);
if (Mask == PTestLikeMask && (PredElementSize == AArch64::ElementSizeB ||
PTest->getOpcode() == AArch64::PTEST_PP_ANY))
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45 changes: 45 additions & 0 deletions llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.mir
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Expand Up @@ -661,3 +661,48 @@ body: |
RET_ReallyLR implicit $w0

...
---
name: cmpeq_nxv16i8_ptest_with_register_class_mismatch
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: ppr }
- { id: 1, class: zpr }
- { id: 2, class: zpr }
- { id: 3, class: ppr_3b }
- { id: 4, class: ppr }
- { id: 5, class: gpr32 }
- { id: 6, class: gpr32 }
liveins:
- { reg: '$z0', virtual-reg: '%1' }
- { reg: '$z1', virtual-reg: '%2' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0:
liveins: $z0, $z1

; CHECK-LABEL: name: cmpeq_nxv16i8_ptest_with_register_class_mismatch
; CHECK: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY [[PTRUE_B]]
; CHECK-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[COPY2]], [[COPY]], [[COPY1]], implicit-def $nzcv
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Can you also have the other case where you have something like:

[[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
[[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
[[COPY2:%[0-9]+]]:ppr = COPY [[PTRUE_B]]
PTEST_PP [[COPY2]], killed [[CMPEQ_PPzZZ_B]], implicit-def $nzcv

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@paulwalker-arm paulwalker-arm Mar 19, 2025 •
edited
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I don't think so because PTRUE_B supports all predicate registers and so at this stage I would expect its virtual register to always be a PPR rather than any of the subclasses.

The scenario can happen after register coalescing but that occurs after the peephole pass in which the PTEST removal is performed.

; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:zpr = COPY $z0
%2:zpr = COPY $z1
%0:ppr = PTRUE_B 31, implicit $vg
%3:ppr_3b = COPY %0
%4:ppr = CMPEQ_PPzZZ_B %3, %1, %2, implicit-def dead $nzcv
PTEST_PP %0, killed %4, implicit-def $nzcv
%5:gpr32 = COPY $wzr
%6:gpr32 = CSINCWr %5, $wzr, 0, implicit $nzcv
$w0 = COPY %6
RET_ReallyLR implicit $w0

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