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[AMDGPU] Extend test coverage for cross RC register coalescing #132137

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Merged
merged 6 commits into from
May 5, 2025
Merged

[AMDGPU] Extend test coverage for cross RC register coalescing #132137

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5c9bac4
debug
jrbyrnes May 1, 2025
c88dcaa
[AMDGPU] Extend test coverage for cross RC register coalescing
jrbyrnes Mar 20, 2025
58ccb88
[AMDGPU] Extend test coverage for cross RC register coalescing
jrbyrnes Mar 20, 2025
8ba7709
Add more coverage
jrbyrnes Mar 25, 2025
8881580
Fix RC constants
jrbyrnes May 5, 2025
c8eeced
Manually fix test
jrbyrnes May 5, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -216,6 +216,7 @@ class GCNIterativeScheduler::OverrideLegacyStrategy {
assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End);
// DAG SUnits are stored using original region's order
// so just use SUnits as the restoring schedule
errs() << "restore order\n";
Sch.scheduleRegion(Rgn, Sch.SUnits, SaveMaxRP);
}
};
Expand Down Expand Up @@ -374,6 +375,10 @@ void GCNIterativeScheduler::scheduleRegion(Region &R, Range &&Schedule,
const GCNRegPressure &MaxRP) {
assert(RegionBegin == R.Begin && RegionEnd == R.End);
assert(LIS != nullptr);
errs() << "Scheedule region R: ";
for (auto I = R.Begin; I != R.End; I++) {
I->dump();
}
#ifndef NDEBUG
const auto SchedMaxRP = getSchedulePressure(R, Schedule);
#endif
Expand Down
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