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[TTI] Use TypeSize in isLoadFromStackSlot and isStoreToStackSlot [nfc] #132244

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Merged
merged 2 commits into from
Mar 20, 2025
Merged

[TTI] Use TypeSize in isLoadFromStackSlot and isStoreToStackSlot [nfc] #132244

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05afb86
[TTI] Use TypeSize in isLoadFromStackSlot and isStoreToStackSlot [nfc]
preames Mar 20, 2025
ff65719
Address review comment
preames Mar 20, 2025
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9 changes: 5 additions & 4 deletions llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TypeSize.h"
#include <array>
#include <cassert>
#include <cstddef>
Expand Down Expand Up @@ -293,8 +294,8 @@ class TargetInstrInfo : public MCInstrInfo {
/// what the load does.
virtual Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
MemBytes = 0;
TypeSize &MemBytes) const {
MemBytes = TypeSize::getZero();
return isLoadFromStackSlot(MI, FrameIndex);
}

Expand Down Expand Up @@ -331,8 +332,8 @@ class TargetInstrInfo : public MCInstrInfo {
/// what the store does.
virtual Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
MemBytes = 0;
TypeSize &MemBytes) const {
MemBytes = TypeSize::getZero();
return isStoreToStackSlot(MI, FrameIndex);
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/StackSlotColoring.cpp
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Expand Up @@ -484,8 +484,8 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) {

Register LoadReg;
Register StoreReg;
unsigned LoadSize = 0;
unsigned StoreSize = 0;
TypeSize LoadSize = TypeSize::getZero();
TypeSize StoreSize = TypeSize::getZero();
if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize)))
continue;
// Skip the ...pseudo debugging... instructions between a load and store.
Expand Down
24 changes: 12 additions & 12 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -95,35 +95,35 @@ MCInst RISCVInstrInfo::getNop() const {

Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
unsigned Dummy;
TypeSize Dummy = TypeSize::getZero();
return isLoadFromStackSlot(MI, FrameIndex, Dummy);
}

Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
TypeSize &MemBytes) const {
switch (MI.getOpcode()) {
default:
return 0;
case RISCV::LB:
case RISCV::LBU:
MemBytes = 1;
MemBytes = TypeSize::getFixed(1);
break;
case RISCV::LH:
case RISCV::LH_INX:
case RISCV::LHU:
case RISCV::FLH:
MemBytes = 2;
MemBytes = TypeSize::getFixed(2);
break;
case RISCV::LW:
case RISCV::LW_INX:
case RISCV::FLW:
case RISCV::LWU:
MemBytes = 4;
MemBytes = TypeSize::getFixed(4);
break;
case RISCV::LD:
case RISCV::FLD:
MemBytes = 8;
MemBytes = TypeSize::getFixed(8);
break;
}

Expand All @@ -138,32 +138,32 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,

Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
unsigned Dummy;
TypeSize Dummy = TypeSize::getZero();
return isStoreToStackSlot(MI, FrameIndex, Dummy);
}

Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
TypeSize &MemBytes) const {
switch (MI.getOpcode()) {
default:
return 0;
case RISCV::SB:
MemBytes = 1;
MemBytes = TypeSize::getFixed(1);
break;
case RISCV::SH:
case RISCV::SH_INX:
case RISCV::FSH:
MemBytes = 2;
MemBytes = TypeSize::getFixed(2);
break;
case RISCV::SW:
case RISCV::SW_INX:
case RISCV::FSW:
MemBytes = 4;
MemBytes = TypeSize::getFixed(4);
break;
case RISCV::SD:
case RISCV::FSD:
MemBytes = 8;
MemBytes = TypeSize::getFixed(8);
break;
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Expand Up @@ -70,11 +70,11 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
unsigned &MemBytes) const override;
TypeSize &MemBytes) const override;
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
unsigned &MemBytes) const override;
TypeSize &MemBytes) const override;

bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;

Expand Down
44 changes: 22 additions & 22 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
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Expand Up @@ -486,21 +486,21 @@ bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
return false;
}

static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
static bool isFrameLoadOpcode(int Opcode, TypeSize &MemBytes) {
switch (Opcode) {
default:
return false;
case X86::MOV8rm:
case X86::KMOVBkm:
case X86::KMOVBkm_EVEX:
MemBytes = 1;
MemBytes = TypeSize::getFixed(1);
return true;
case X86::MOV16rm:
case X86::KMOVWkm:
case X86::KMOVWkm_EVEX:
case X86::VMOVSHZrm:
case X86::VMOVSHZrm_alt:
MemBytes = 2;
MemBytes = TypeSize::getFixed(2);
return true;
case X86::MOV32rm:
case X86::MOVSSrm:
Expand All @@ -511,7 +511,7 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
case X86::VMOVSSZrm_alt:
case X86::KMOVDkm:
case X86::KMOVDkm_EVEX:
MemBytes = 4;
MemBytes = TypeSize::getFixed(4);
return true;
case X86::MOV64rm:
case X86::LD_Fp64m:
Expand All @@ -525,7 +525,7 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
case X86::MMX_MOVQ64rm:
case X86::KMOVQkm:
case X86::KMOVQkm_EVEX:
MemBytes = 8;
MemBytes = TypeSize::getFixed(8);
return true;
case X86::MOVAPSrm:
case X86::MOVUPSrm:
Expand All @@ -551,7 +551,7 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
case X86::VMOVDQU32Z128rm:
case X86::VMOVDQA64Z128rm:
case X86::VMOVDQU64Z128rm:
MemBytes = 16;
MemBytes = TypeSize::getFixed(16);
return true;
case X86::VMOVAPSYrm:
case X86::VMOVUPSYrm:
Expand All @@ -571,7 +571,7 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
case X86::VMOVDQU32Z256rm:
case X86::VMOVDQA64Z256rm:
case X86::VMOVDQU64Z256rm:
MemBytes = 32;
MemBytes = TypeSize::getFixed(32);
return true;
case X86::VMOVAPSZrm:
case X86::VMOVUPSZrm:
Expand All @@ -583,33 +583,33 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
case X86::VMOVDQU32Zrm:
case X86::VMOVDQA64Zrm:
case X86::VMOVDQU64Zrm:
MemBytes = 64;
MemBytes = TypeSize::getFixed(64);
return true;
}
}

static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
static bool isFrameStoreOpcode(int Opcode, TypeSize &MemBytes) {
switch (Opcode) {
default:
return false;
case X86::MOV8mr:
case X86::KMOVBmk:
case X86::KMOVBmk_EVEX:
MemBytes = 1;
MemBytes = TypeSize::getFixed(1);
return true;
case X86::MOV16mr:
case X86::KMOVWmk:
case X86::KMOVWmk_EVEX:
case X86::VMOVSHZmr:
MemBytes = 2;
MemBytes = TypeSize::getFixed(2);
return true;
case X86::MOV32mr:
case X86::MOVSSmr:
case X86::VMOVSSmr:
case X86::VMOVSSZmr:
case X86::KMOVDmk:
case X86::KMOVDmk_EVEX:
MemBytes = 4;
MemBytes = TypeSize::getFixed(4);
return true;
case X86::MOV64mr:
case X86::ST_FpP64m:
Expand All @@ -621,7 +621,7 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
case X86::MMX_MOVNTQmr:
case X86::KMOVQmk:
case X86::KMOVQmk_EVEX:
MemBytes = 8;
MemBytes = TypeSize::getFixed(8);
return true;
case X86::MOVAPSmr:
case X86::MOVUPSmr:
Expand All @@ -647,7 +647,7 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
case X86::VMOVDQU64Z128mr:
case X86::VMOVDQU8Z128mr:
case X86::VMOVDQU16Z128mr:
MemBytes = 16;
MemBytes = TypeSize::getFixed(16);
return true;
case X86::VMOVUPSYmr:
case X86::VMOVAPSYmr:
Expand All @@ -667,7 +667,7 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
case X86::VMOVDQU32Z256mr:
case X86::VMOVDQA64Z256mr:
case X86::VMOVDQU64Z256mr:
MemBytes = 32;
MemBytes = TypeSize::getFixed(32);
return true;
case X86::VMOVUPSZmr:
case X86::VMOVAPSZmr:
Expand All @@ -679,21 +679,21 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
case X86::VMOVDQU32Zmr:
case X86::VMOVDQA64Zmr:
case X86::VMOVDQU64Zmr:
MemBytes = 64;
MemBytes = TypeSize::getFixed(64);
return true;
}
return false;
}

Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
unsigned Dummy;
TypeSize Dummy = TypeSize::getZero();
return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
}

Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
TypeSize &MemBytes) const {
if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
return MI.getOperand(0).getReg();
Expand All @@ -702,7 +702,7 @@ Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,

Register X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
unsigned Dummy;
TypeSize Dummy = TypeSize::getZero();
if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
return Reg;
Expand All @@ -720,13 +720,13 @@ Register X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,

Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
unsigned Dummy;
TypeSize Dummy = TypeSize::getZero();
return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
}

Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
TypeSize &MemBytes) const {
if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
isFrameOperand(MI, 0, FrameIndex))
Expand All @@ -736,7 +736,7 @@ Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,

Register X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
unsigned Dummy;
TypeSize Dummy = TypeSize::getZero();
if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
return Reg;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86InstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -276,7 +276,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
int &FrameIndex) const override;
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const override;
TypeSize &MemBytes) const override;
/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
/// stack locations as well. This uses a heuristic so it isn't
/// reliable for correctness.
Expand All @@ -287,7 +287,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
int &FrameIndex) const override;
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const override;
TypeSize &MemBytes) const override;
/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
/// stack locations as well. This uses a heuristic so it isn't
/// reliable for correctness.
Expand Down
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