Skip to content

[AVR] Fix a bug in selection of ANY_EXTEND #132398

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Mar 26, 2025
Merged

[AVR] Fix a bug in selection of ANY_EXTEND #132398

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
0056c92
[AVR] Fix a bug in selection of ANY_EXTEND
benshi001 Mar 21, 2025
eac3744
[AVR][NFC] Supplement a test to issue #132203
benshi001 Mar 23, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 4 additions & 4 deletions llvm/lib/Target/AVR/AVRInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1750,10 +1750,10 @@ def : Pat<(AVRcall(i16 tglobaladdr:$dst)), (RCALLk tglobaladdr:$dst)>;
def : Pat<(AVRcall(i16 texternalsym:$dst)), (RCALLk texternalsym:$dst)>;

// `anyext`
def : Pat<(i16(anyext i8
: $src)),
(INSERT_SUBREG(i16(IMPLICIT_DEF)), i8
: $src, sub_lo)>;
// FIMXE: Using INSERT_SUBREG is more efficient, but leads to issue #132203.
def : Pat<(i16(anyext i8:$src)),
// (INSERT_SUBREG(i16(IMPLICIT_DEF)), i8:$src, sub_lo)>;
(ZEXT i8:$src)>;

// `trunc`
def : Pat<(i8(trunc i16 : $src)), (EXTRACT_SUBREG i16 : $src, sub_lo)>;
Expand Down
21 changes: 12 additions & 9 deletions llvm/test/CodeGen/AVR/hardware-mul.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,19 +21,22 @@ define i16 @mult16(i16 %a, i16 %b) {
; CHECK-NEXT: mov r25, r0
; CHECK-NEXT: clr r1
; CHECK-NEXT: mul r22, r24
; CHECK-NEXT: mov r20, r0
; CHECK-NEXT: mov r18, r1
; CHECK-NEXT: mov r18, r0
; CHECK-NEXT: mov r19, r1
; CHECK-NEXT: clr r1
; CHECK-NEXT: add r18, r25
; CHECK-NEXT: add r19, r25
; CHECK-NEXT: muls r23, r24
; CHECK-NEXT: clr r1
; CHECK-NEXT: add r18, r0
; CHECK-NEXT: mov r19, r18
; CHECK-NEXT: clr r18
; CHECK-NEXT: mov r24, r20
; CHECK-NEXT: mov r24, r0
; CHECK-NEXT: add r24, r19
; CHECK-NEXT: mov r20, r24
; CHECK-NEXT: clr r21
; CHECK-NEXT: mov r21, r20
; CHECK-NEXT: clr r20
; CHECK-NEXT: mov r24, r18
; CHECK-NEXT: clr r25
; CHECK-NEXT: or r24, r18
; CHECK-NEXT: or r25, r19
; CHECK-NEXT: or r24, r20
; CHECK-NEXT: or r25, r21
; CHECK-NEXT: ret
%mul = mul nsw i16 %b, %a
ret i16 %mul
Expand Down
29 changes: 18 additions & 11 deletions llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,10 @@ define void @add_b_i8(i8 signext %0, i8 signext %1) {
; CHECK: ; %bb.0:
; CHECK-NEXT: mov r20, r22
; CHECK-NEXT: mov r22, r24
; CHECK-NEXT: mov r30, r22
; CHECK-NEXT: mov r24, r22
; CHECK-NEXT: clr r25
; CHECK-NEXT: mov r30, r24
; CHECK-NEXT: mov r31, r25
; CHECK-NEXT: ;APP
; CHECK-NEXT: mov r30, r30
; CHECK-NEXT: add r30, r20
Expand Down Expand Up @@ -224,14 +227,16 @@ define void @add_b_i16(i16 signext %0, i16 signext %1) {
define void @add_e_i8(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: add_e_i8:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov r30, r22
; CHECK-NEXT: mov r20, r22
; CHECK-NEXT: mov r22, r24
; CHECK-NEXT: mov r26, r22
; CHECK-NEXT: clr r27
; CHECK-NEXT: mov r30, r20
; CHECK-NEXT: clr r31
; CHECK-NEXT: ;APP
; CHECK-NEXT: mov r26, r26
; CHECK-NEXT: add r26, r30
; CHECK-NEXT: ;NO_APP
; CHECK-NEXT: mov r20, r30
; CHECK-NEXT: mov r24, r26
; CHECK-NEXT: rcall foo8
; CHECK-NEXT: ret
Expand Down Expand Up @@ -286,14 +291,16 @@ define void @add_t_i8(i8 signext %0, i8 signext %1) {
define void @add_w_i8(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: add_w_i8:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov r26, r22
; CHECK-NEXT: mov r30, r24
; CHECK-NEXT: mov r20, r22
; CHECK-NEXT: mov r22, r24
; CHECK-NEXT: mov r24, r22
; CHECK-NEXT: clr r25
; CHECK-NEXT: mov r30, r20
; CHECK-NEXT: clr r31
; CHECK-NEXT: ;APP
; CHECK-NEXT: mov r24, r30
; CHECK-NEXT: add r24, r26
; CHECK-NEXT: mov r24, r24
; CHECK-NEXT: add r24, r30
; CHECK-NEXT: ;NO_APP
; CHECK-NEXT: mov r22, r30
; CHECK-NEXT: mov r20, r26
; CHECK-NEXT: rcall foo8
; CHECK-NEXT: ret
%3 = tail call i8 asm sideeffect "mov $0, $1\0Aadd $0, $2", "=w,w,w"(i8 %0, i8 %1)
Expand Down Expand Up @@ -333,9 +340,9 @@ define void @add_xyz_i8(i8 signext %0, i8 signext %1) {
; CHECK-NEXT: mov r20, r22
; CHECK-NEXT: mov r22, r24
; CHECK-NEXT: mov r28, r22
; CHECK-NEXT: mov r29, r23
; CHECK-NEXT: clr r29
; CHECK-NEXT: mov r26, r20
; CHECK-NEXT: mov r27, r21
; CHECK-NEXT: clr r27
; CHECK-NEXT: ;APP
; CHECK-NEXT: mov r30, r28
; CHECK-NEXT: add r30, r26
Expand Down
66 changes: 66 additions & 0 deletions llvm/test/CodeGen/AVR/issue-132203.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,66 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=avr -mattr=+movw | FileCheck %s --check-prefix=MOVW
; RUN: llc < %s -mtriple=avr -mattr=-movw | FileCheck %s --check-prefix=NOMOVW

define i16 @food(ptr %this) {
; MOVW-LABEL: food:
; MOVW: ; %bb.0: ; %entry
; MOVW-NEXT: movw r30, r24
; MOVW-NEXT: ldd r24, Z+25
; MOVW-NEXT: clr r25
; MOVW-NEXT: ldd r18, Z+26
; MOVW-NEXT: clr r19
; MOVW-NEXT: sub r24, r18
; MOVW-NEXT: sbc r25, r19
; MOVW-NEXT: andi r24, 63
; MOVW-NEXT: andi r25, 0
; MOVW-NEXT: ret
;
; NOMOVW-LABEL: food:
; NOMOVW: ; %bb.0: ; %entry
; NOMOVW-NEXT: mov r30, r24
; NOMOVW-NEXT: mov r31, r25
; NOMOVW-NEXT: ldd r24, Z+25
; NOMOVW-NEXT: clr r25
; NOMOVW-NEXT: ldd r18, Z+26
; NOMOVW-NEXT: clr r19
; NOMOVW-NEXT: sub r24, r18
; NOMOVW-NEXT: sbc r25, r19
; NOMOVW-NEXT: andi r24, 63
; NOMOVW-NEXT: andi r25, 0
; NOMOVW-NEXT: ret
entry:
%_rx_buffer_head = getelementptr inbounds nuw i8, ptr %this, i16 25
%0 = load volatile i8, ptr %_rx_buffer_head
%conv = zext i8 %0 to i16
%_rx_buffer_tail = getelementptr inbounds nuw i8, ptr %this, i16 26
%1 = load volatile i8, ptr %_rx_buffer_tail
%conv2 = zext i8 %1 to i16
%sub = sub nsw i16 %conv, %conv2
%rem = and i16 %sub, 63
ret i16 %rem
}

define i16 @fooe(i8 %a) {
; MOVW-LABEL: fooe:
; MOVW: ; %bb.0:
; MOVW-NEXT: clr r25
; MOVW-NEXT: subi r24, 0
; MOVW-NEXT: sbci r25, 1
; MOVW-NEXT: andi r24, 1
; MOVW-NEXT: andi r25, 0
; MOVW-NEXT: ret
;
; NOMOVW-LABEL: fooe:
; NOMOVW: ; %bb.0:
; NOMOVW-NEXT: clr r25
; NOMOVW-NEXT: subi r24, 0
; NOMOVW-NEXT: sbci r25, 1
; NOMOVW-NEXT: andi r24, 1
; NOMOVW-NEXT: andi r25, 0
; NOMOVW-NEXT: ret
%1 = zext i8 %a to i16
%2 = sub i16 %1, 256
%3 = and i16 %2, 1
ret i16 %3
}