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[RISCV] Remove experimental from Sdext and Sdtrig which are ratified. #132529

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Merged
merged 4 commits into from
Mar 24, 2025
Merged

[RISCV] Remove experimental from Sdext and Sdtrig which are ratified. #132529

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3b30343
[RISCV] Remove experimental from Sdext and Sdtrig which are ratified.
topperc Mar 22, 2025
c68251d
Merge remote-tracking branch 'origin/main' into pr/sdext-experimental
topperc Mar 24, 2025
8cefd3b
fixup! Update print-supported-extensions-riscv.c
topperc Mar 24, 2025
8a5f2ea
fixup! update features-info.ll
topperc Mar 24, 2025
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4 changes: 2 additions & 2 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Expand Up @@ -112,6 +112,8 @@
// CHECK-NEXT: zvl8192b 1.0 'Zvl8192b' (Minimum Vector Length 8192)
// CHECK-NEXT: zhinx 1.0 'Zhinx' (Half Float in Integer)
// CHECK-NEXT: zhinxmin 1.0 'Zhinxmin' (Half Float in Integer Minimal)
// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers)
// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
Expand Down Expand Up @@ -191,8 +193,6 @@
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product)
// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers)
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -869,9 +869,9 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,

// Supervisor extensions

def FeatureStdExtSdext : RISCVExperimentalExtension<1, 0, "External debugger">;
def FeatureStdExtSdext : RISCVExtension<1, 0, "External debugger">;

def FeatureStdExtSdtrig : RISCVExperimentalExtension<1, 0, "Debugger triggers">;
def FeatureStdExtSdtrig : RISCVExtension<1, 0, "Debugger triggers">;

def FeatureStdExtShgatpa
: RISCVExtension<1, 0,
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -316,8 +316,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s


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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/features-info.ll
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Expand Up @@ -17,8 +17,6 @@
; CHECK-NEXT: experimental - Experimental intrinsics.
; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)).
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK-NEXT: experimental-sdext - 'Sdext' (External debugger).
; CHECK-NEXT: experimental-sdtrig - 'Sdtrig' (Debugger triggers).
; CHECK-NEXT: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level).
; CHECK-NEXT: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
Expand Down Expand Up @@ -115,6 +113,8 @@
; CHECK-NEXT: rvi20u32 - RISC-V rvi20u32 profile.
; CHECK-NEXT: rvi20u64 - RISC-V rvi20u64 profile.
; CHECK-NEXT: save-restore - Enable save/restore..
; CHECK-NEXT: sdext - 'Sdext' (External debugger).
; CHECK-NEXT: sdtrig - 'Sdtrig' (Debugger triggers).
; CHECK-NEXT: sha - 'Sha' (Augmented Hypervisor).
; CHECK-NEXT: shcounterenw - 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero).
; CHECK-NEXT: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare).
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4 changes: 2 additions & 2 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1065,6 +1065,8 @@ R"(All available -march extensions for RISC-V
zvl8192b 1.0
zhinx 1.0
zhinxmin 1.0
sdext 1.0
sdtrig 1.0
sha 1.0
shcounterenw 1.0
shgatpa 1.0
Expand Down Expand Up @@ -1144,8 +1146,6 @@ Experimental extensions
zvbc32e 0.7
zvkgs 0.7
zvqdotq 0.0
sdext 1.0
sdtrig 1.0
smctr 1.0
ssctr 1.0
svukte 0.3
Expand Down