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[MC] Account for AcquireAtCycle in getReciprocalThroughput #132653

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merged 2 commits into from
Mar 24, 2025
Merged

[MC] Account for AcquireAtCycle in getReciprocalThroughput #132653

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6fde28d
[MC] Account for AcquireAtCycle in getReciprocalThroughput
mshockwave Mar 24, 2025
3ede14c
fixup! Address review comments
mshockwave Mar 24, 2025
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15 changes: 9 additions & 6 deletions llvm/lib/MC/MCSchedule.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -96,19 +96,22 @@ int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
double
MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
const MCSchedClassDesc &SCDesc) {
std::optional<double> Throughput;
std::optional<double> MinThroughput;
const MCSchedModel &SM = STI.getSchedModel();
const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
for (; I != E; ++I) {
if (!I->ReleaseAtCycle)
if (!I->ReleaseAtCycle || I->ReleaseAtCycle == I->AcquireAtCycle)
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does I->ReleaseAtCycle == I->AcquireAtCycle actually happen?

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does I->ReleaseAtCycle == I->AcquireAtCycle actually happen?

It's allowed:

llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp

Line 4647 in 70c325b

// Zero resource usage is allowed by TargetSchedule.td but we do not construct

And it indeed happens:

llvm-project/llvm/lib/Target/AArch64/AArch64SchedA510.td

Line 507 in 70c325b

def : InstRW<[CortexA510MCWrite<4, 0, CortexA510UnitVMC>], (instrs PMULLv1i64, PMULLv2i64)>;

(the second template argument is ReleaseAtCycle, with AcquireAtCycle left to be default value of 0)

It's not clear to me why they (CortexA510) want both ReleaseAtCycle and AcquireAtCycle to be zero. Maybe they want to exclude these instructions completely from MachineScheduler.

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I believe its allowed in the case that the resource needs to be available but does not use it. This could happen in a scenario where some other instruction might make it busy.

continue;
assert(I->ReleaseAtCycle > I->AcquireAtCycle && "invalid resource segment");
unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
double Temp = NumUnits * 1.0 / I->ReleaseAtCycle;
Throughput = Throughput ? std::min(*Throughput, Temp) : Temp;
double Throughput =
double(NumUnits) / double(I->ReleaseAtCycle - I->AcquireAtCycle);
MinThroughput =
MinThroughput ? std::min(*MinThroughput, Throughput) : Throughput;
}
if (Throughput)
return 1.0 / *Throughput;
if (MinThroughput)
return 1.0 / *MinThroughput;

// If no throughput value was calculated, assume that we can execute at the
// maximum issue width scaled by number of micro-ops for the schedule class.
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4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-lmul-instruments.s
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Original file line number Diff line number Diff line change
Expand Up @@ -28,9 +28,9 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
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4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-sew-instruments.s
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Original file line number Diff line number Diff line change
Expand Up @@ -29,9 +29,9 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
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6 changes: 3 additions & 3 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/disable-im.s
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Original file line number Diff line number Diff line change
Expand Up @@ -31,11 +31,11 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
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4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/fractional-lmul-data.s
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Original file line number Diff line number Diff line change
Expand Up @@ -29,9 +29,9 @@ vdiv.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 56 57.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 56 56.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 30 31.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 30 30.00 vdiv.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
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2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-at-start.s
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
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4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-in-middle.s
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Original file line number Diff line number Diff line change
Expand Up @@ -25,9 +25,9 @@ vadd.vv v12, v12, v12
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 1.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
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2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-in-region.s
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
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2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-straddles-region.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-lmul-instruments.s
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Expand Up @@ -33,13 +33,13 @@ vsub.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: 1 4 9.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 9.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 4 8.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 8.00 vsub.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-sew-instruments.s
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Original file line number Diff line number Diff line change
Expand Up @@ -34,13 +34,13 @@ vdivu.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 115.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 114.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m1, tu, mu
# CHECK-NEXT: 1 112 113.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 112 113.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 112 112.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 112 112.00 vdivu.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,8 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/no-vsetvli-to-start.s
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Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,9 @@ vadd.vv v12, v12, v12
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
Expand Down
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