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[llvm][CodeGen] update live intervals for ModuloScheduleExpanderMVE #132677

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merged 6 commits into from
Apr 10, 2025
Merged

[llvm][CodeGen] update live intervals for ModuloScheduleExpanderMVE #132677

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b825cf1
[llvm][CodeGen] update live intarvals for ModuloScheduleExpanderMVE
huaatian Mar 24, 2025
5c3d1dc
[CodeGen] Modifications made based on review comments 1
huaatian Mar 25, 2025
35b17ab
[CodeGen] Modifications made based on review comments 2
huaatian Mar 25, 2025
5cc1fea
[llvm][CodeGen] Modifications made based on review comments 3
huaatian Apr 7, 2025
8fc57ca
[llvm][CodeGen] Modifications made based on review comments 4
huaatian Apr 8, 2025
c3efa2e
[llvm][CodeGen] Modifications made based on review comments 5
huaatian Apr 8, 2025
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69 changes: 44 additions & 25 deletions llvm/lib/CodeGen/ModuloSchedule.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2159,7 +2159,8 @@ MachineInstr *ModuloScheduleExpanderMVE::cloneInstr(MachineInstr *OldMI) {
/// If it is already dedicated exit, return it. Otherwise, insert a new
/// block between them and return the new block.
static MachineBasicBlock *createDedicatedExit(MachineBasicBlock *Loop,
MachineBasicBlock *Exit) {
MachineBasicBlock *Exit,
LiveIntervals &LIS) {
if (Exit->pred_size() == 1)
return Exit;

Expand All @@ -2169,6 +2170,7 @@ static MachineBasicBlock *createDedicatedExit(MachineBasicBlock *Loop,
MachineBasicBlock *NewExit =
MF->CreateMachineBasicBlock(Loop->getBasicBlock());
MF->insert(Loop->getIterator(), NewExit);
LIS.insertMBBInMaps(NewExit);

MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
SmallVector<MachineOperand, 4> Cond;
Expand Down Expand Up @@ -2304,12 +2306,17 @@ void ModuloScheduleExpanderMVE::generatePipelinedLoop() {
NewPreheader = MF.CreateMachineBasicBlock(OrigKernel->getBasicBlock());

MF.insert(OrigKernel->getIterator(), Check);
LIS.insertMBBInMaps(Check);
MF.insert(OrigKernel->getIterator(), Prolog);
LIS.insertMBBInMaps(Prolog);
MF.insert(OrigKernel->getIterator(), NewKernel);
LIS.insertMBBInMaps(NewKernel);
MF.insert(OrigKernel->getIterator(), Epilog);
LIS.insertMBBInMaps(Epilog);
MF.insert(OrigKernel->getIterator(), NewPreheader);
LIS.insertMBBInMaps(NewPreheader);

NewExit = createDedicatedExit(OrigKernel, OrigExit);
NewExit = createDedicatedExit(OrigKernel, OrigExit, LIS);

NewPreheader->transferSuccessorsAndUpdatePHIs(OrigPreheader);
TII->insertUnconditionalBranch(*NewPreheader, OrigKernel, DebugLoc());
Expand Down Expand Up @@ -2393,9 +2400,10 @@ void ModuloScheduleExpanderMVE::updateInstrUse(
UseMO.setReg(NewReg);
else {
Register SplitReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg));
BuildMI(*OrigKernel, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
SplitReg)
.addReg(NewReg);
MachineInstr *NewCopy = BuildMI(*OrigKernel, MI, MI->getDebugLoc(),
TII->get(TargetOpcode::COPY), SplitReg)
.addReg(NewReg);
LIS.InsertMachineInstrInMaps(*NewCopy);
UseMO.setReg(SplitReg);
}
}
Expand Down Expand Up @@ -2479,12 +2487,14 @@ void ModuloScheduleExpanderMVE::generatePhi(

assert(CorrespondReg.isValid());
Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg));
BuildMI(*NewKernel, NewKernel->getFirstNonPHI(), DebugLoc(),
TII->get(TargetOpcode::PHI), PhiReg)
.addReg(NewReg->second)
.addMBB(NewKernel)
.addReg(CorrespondReg)
.addMBB(Prolog);
MachineInstr *NewPhi =
BuildMI(*NewKernel, NewKernel->getFirstNonPHI(), DebugLoc(),
TII->get(TargetOpcode::PHI), PhiReg)
.addReg(NewReg->second)
.addMBB(NewKernel)
.addReg(CorrespondReg)
.addMBB(Prolog);
LIS.InsertMachineInstrInMaps(*NewPhi);
PhiVRMap[UnrollNum][OrigReg] = PhiReg;
}
}
Expand Down Expand Up @@ -2522,18 +2532,22 @@ void ModuloScheduleExpanderMVE::mergeRegUsesAfterPipeline(Register OrigReg,
// remaining iterations) with the route that execute the original loop.
if (!UsesAfterLoop.empty()) {
Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg));
BuildMI(*NewExit, NewExit->getFirstNonPHI(), DebugLoc(),
TII->get(TargetOpcode::PHI), PhiReg)
.addReg(OrigReg)
.addMBB(OrigKernel)
.addReg(NewReg)
.addMBB(Epilog);
MachineInstr *NewPhi =
BuildMI(*NewExit, NewExit->getFirstNonPHI(), DebugLoc(),
TII->get(TargetOpcode::PHI), PhiReg)
.addReg(OrigReg)
.addMBB(OrigKernel)
.addReg(NewReg)
.addMBB(Epilog);
LIS.InsertMachineInstrInMaps(*NewPhi);

for (MachineOperand *MO : UsesAfterLoop)
MO->setReg(PhiReg);

if (!LIS.hasInterval(PhiReg))
LIS.createEmptyInterval(PhiReg);
// The interval of OrigReg is invalid and should be recalculated when
// LiveInterval::getInterval() is called.
if (LIS.hasInterval(OrigReg))
LIS.removeInterval(OrigReg);
}

// Merge routes from the pipelined loop and the bypassed route before the
Expand All @@ -2543,12 +2557,14 @@ void ModuloScheduleExpanderMVE::mergeRegUsesAfterPipeline(Register OrigReg,
Register InitReg, LoopReg;
getPhiRegs(*Phi, OrigKernel, InitReg, LoopReg);
Register NewInit = MRI.createVirtualRegister(MRI.getRegClass(InitReg));
BuildMI(*NewPreheader, NewPreheader->getFirstNonPHI(), Phi->getDebugLoc(),
TII->get(TargetOpcode::PHI), NewInit)
.addReg(InitReg)
.addMBB(Check)
.addReg(NewReg)
.addMBB(Epilog);
MachineInstr *NewPhi =
BuildMI(*NewPreheader, NewPreheader->getFirstNonPHI(),
Phi->getDebugLoc(), TII->get(TargetOpcode::PHI), NewInit)
.addReg(InitReg)
.addMBB(Check)
.addReg(NewReg)
.addMBB(Epilog);
LIS.InsertMachineInstrInMaps(*NewPhi);
replacePhiSrc(*Phi, InitReg, NewInit, NewPreheader);
}
}
Expand All @@ -2571,6 +2587,7 @@ void ModuloScheduleExpanderMVE::generateProlog(
updateInstrDef(NewMI, PrologVRMap[PrologNum], false);
NewMIMap[NewMI] = {PrologNum, StageNum};
Prolog->push_back(NewMI);
LIS.InsertMachineInstrInMaps(*NewMI);
}
}

Expand Down Expand Up @@ -2609,6 +2626,7 @@ void ModuloScheduleExpanderMVE::generateKernel(
generatePhi(MI, UnrollNum, PrologVRMap, KernelVRMap, PhiVRMap);
NewMIMap[NewMI] = {UnrollNum, StageNum};
NewKernel->push_back(NewMI);
LIS.InsertMachineInstrInMaps(*NewMI);
}
}

Expand Down Expand Up @@ -2647,6 +2665,7 @@ void ModuloScheduleExpanderMVE::generateEpilog(
updateInstrDef(NewMI, EpilogVRMap[EpilogNum], StageNum - 1 == EpilogNum);
NewMIMap[NewMI] = {EpilogNum, StageNum};
Epilog->push_back(NewMI);
LIS.InsertMachineInstrInMaps(*NewMI);
}
}

Expand Down
222 changes: 222 additions & 0 deletions llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,222 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc --mtriple=aarch64 %s -run-pass=pipeliner -pipeliner-mve-cg -o -| FileCheck %s

...
---
name: foo
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.13(0x80000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $xzr
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[COPY1]]
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.13:
; CHECK-NEXT: successors: %bb.14(0x80000000), %bb.15(0x00000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0
; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = nsw SUBSXri [[SUBREG_TO_REG]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64all = COPY [[SUBSXri]]
; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: Bcc 0, %bb.15, implicit $nzcv
; CHECK-NEXT: B %bb.14
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.14:
; CHECK-NEXT: successors: %bb.15(0x04000000), %bb.14(0x7c000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY3]], %bb.13, %73, %bb.14
; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr64 = PHI [[SUBREG_TO_REG1]], %bb.13, %72, %bb.14
; CHECK-NEXT: [[PHI2:%[0-9]+]]:fpr64 = PHI [[LDRDui]], %bb.13, %70, %bb.14
; CHECK-NEXT: STRDui [[PHI2]], [[COPY]], 0
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0
; CHECK-NEXT: [[SUBSXri1:%[0-9]+]]:gpr64 = nsw SUBSXri [[PHI]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64all = COPY [[SUBSXri1]]
; CHECK-NEXT: Bcc 1, %bb.14, implicit $nzcv
; CHECK-NEXT: B %bb.15
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.15:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI3:%[0-9]+]]:gpr64 = PHI [[COPY2]], %bb.13, [[PHI1]], %bb.14
; CHECK-NEXT: [[PHI4:%[0-9]+]]:fpr64 = PHI [[LDRDui]], %bb.13, [[LDRDui1]], %bb.14
; CHECK-NEXT: STRDui [[PHI4]], [[COPY]], 0
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: CBNZX [[PHI3]], %bb.3
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
; CHECK-NEXT: successors: %bb.7(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI5:%[0-9]+]]:fpr64 = PHI [[FMOVD0_]], %bb.4, %62, %bb.12
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr64all = COPY $xzr
; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr64common = COPY [[COPY5]]
; CHECK-NEXT: B %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7:
; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.11(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64common = ADDSXri [[COPY6]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 3, implicit $nzcv
; CHECK-NEXT: [[ADDSXri1:%[0-9]+]]:gpr64common = ADDSXri [[ADDSXri]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr1:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr]], [[CSINCXr]], 3, implicit $nzcv
; CHECK-NEXT: [[ADDSXri2:%[0-9]+]]:gpr64common = ADDSXri [[ADDSXri1]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr2:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr1]], [[CSINCXr1]], 3, implicit $nzcv
; CHECK-NEXT: [[ADDSXri3:%[0-9]+]]:gpr64 = ADDSXri [[ADDSXri2]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr3:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr2]], [[CSINCXr2]], 3, implicit $nzcv
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr3]], 0, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.8, implicit $nzcv
; CHECK-NEXT: B %bb.11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8:
; CHECK-NEXT: successors: %bb.9(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADDSXri4:%[0-9]+]]:gpr64 = ADDSXri [[COPY6]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY6]], 61, 60
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr64common = COPY [[ADDSXri4]]
; CHECK-NEXT: [[LDRDui2:%[0-9]+]]:fpr64 = LDRDui [[UBFMXri]], 1
; CHECK-NEXT: [[ADDSXri5:%[0-9]+]]:gpr64 = ADDSXri [[COPY7]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[UBFMXri1:%[0-9]+]]:gpr64common = UBFMXri [[COPY7]], 61, 60
; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr64all = COPY [[ADDSXri5]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.9:
; CHECK-NEXT: successors: %bb.9(0x40000000), %bb.10(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI6:%[0-9]+]]:gpr64 = PHI %38, %bb.9, [[ADDSXri4]], %bb.8
; CHECK-NEXT: [[PHI7:%[0-9]+]]:gpr64common = PHI %40, %bb.9, [[UBFMXri]], %bb.8
; CHECK-NEXT: [[PHI8:%[0-9]+]]:gpr64all = PHI %43, %bb.9, [[COPY7]], %bb.8
; CHECK-NEXT: [[PHI9:%[0-9]+]]:fpr64 = PHI %45, %bb.9, [[LDRDui2]], %bb.8
; CHECK-NEXT: [[PHI10:%[0-9]+]]:gpr64 = PHI %47, %bb.9, [[ADDSXri5]], %bb.8
; CHECK-NEXT: [[PHI11:%[0-9]+]]:gpr64common = PHI %49, %bb.9, [[UBFMXri1]], %bb.8
; CHECK-NEXT: [[PHI12:%[0-9]+]]:fpr64 = PHI %51, %bb.9, [[PHI5]], %bb.8
; CHECK-NEXT: [[PHI13:%[0-9]+]]:gpr64common = PHI %53, %bb.9, [[COPY8]], %bb.8
; CHECK-NEXT: [[LDRDui3:%[0-9]+]]:fpr64 = LDRDui [[PHI11]], 1
; CHECK-NEXT: [[ADDSXri6:%[0-9]+]]:gpr64 = ADDSXri [[PHI13]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[UBFMXri2:%[0-9]+]]:gpr64common = UBFMXri [[PHI13]], 61, 60
; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI12]], [[PHI9]], implicit $fpcr
; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr64common = COPY [[ADDSXri6]]
; CHECK-NEXT: [[LDRDui4:%[0-9]+]]:fpr64 = LDRDui [[UBFMXri2]], 1
; CHECK-NEXT: [[ADDSXri7:%[0-9]+]]:gpr64common = ADDSXri [[COPY9]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[UBFMXri3:%[0-9]+]]:gpr64common = UBFMXri [[COPY9]], 61, 60
; CHECK-NEXT: [[FADDDrr1:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FADDDrr]], [[LDRDui3]], implicit $fpcr
; CHECK-NEXT: [[COPY10:%[0-9]+]]:gpr64all = COPY [[ADDSXri7]]
; CHECK-NEXT: [[CSINCXr4:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 3, implicit $nzcv
; CHECK-NEXT: [[ADDSXri8:%[0-9]+]]:gpr64 = ADDSXri [[ADDSXri7]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr5:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr4]], [[CSINCXr4]], 3, implicit $nzcv
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr5]], 0, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.9, implicit $nzcv
; CHECK-NEXT: B %bb.10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.10:
; CHECK-NEXT: successors: %bb.11(0x40000000), %bb.12(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LDRDui5:%[0-9]+]]:fpr64 = LDRDui [[UBFMXri3]], 1
; CHECK-NEXT: [[FADDDrr2:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FADDDrr1]], [[LDRDui4]], implicit $fpcr
; CHECK-NEXT: [[FADDDrr3:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FADDDrr2]], [[LDRDui5]], implicit $fpcr
; CHECK-NEXT: [[ADDSXri9:%[0-9]+]]:gpr64 = ADDSXri [[COPY9]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr6:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 3, implicit $nzcv
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr6]], 0, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.11, implicit $nzcv
; CHECK-NEXT: B %bb.12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.11:
; CHECK-NEXT: successors: %bb.6(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI14:%[0-9]+]]:gpr64common = PHI [[COPY6]], %bb.7, [[COPY10]], %bb.10
; CHECK-NEXT: [[PHI15:%[0-9]+]]:fpr64 = PHI [[PHI5]], %bb.7, [[FADDDrr3]], %bb.10
; CHECK-NEXT: B %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.12:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI16:%[0-9]+]]:fpr64 = PHI %13, %bb.6, [[FADDDrr3]], %bb.10
; CHECK-NEXT: B %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6:
; CHECK-NEXT: successors: %bb.12(0x04000000), %bb.6(0x7c000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI17:%[0-9]+]]:gpr64common = PHI [[PHI14]], %bb.11, %17, %bb.6
; CHECK-NEXT: [[PHI18:%[0-9]+]]:fpr64 = PHI [[PHI15]], %bb.11, %13, %bb.6
; CHECK-NEXT: [[UBFMXri4:%[0-9]+]]:gpr64common = UBFMXri [[PHI17]], 61, 60
; CHECK-NEXT: [[LDRDui6:%[0-9]+]]:fpr64 = LDRDui [[UBFMXri4]], 1
; CHECK-NEXT: [[FADDDrr4:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI18]], [[LDRDui6]], implicit $fpcr
; CHECK-NEXT: [[ADDSXri10:%[0-9]+]]:gpr64 = ADDSXri [[PHI17]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr64all = COPY [[ADDSXri10]]
; CHECK-NEXT: Bcc 2, %bb.12, implicit $nzcv
; CHECK-NEXT: B %bb.6
bb.0:
successors: %bb.1(0x80000000)
liveins: $x0

%0:gpr64common = COPY $x0
%1:gpr64sp = COPY $xzr
%2:gpr64all = COPY %1
%3:gpr32 = MOVi32imm 1
%4:gpr64all = SUBREG_TO_REG 0, %3, %subreg.sub_32

bb.1:
successors: %bb.2(0x04000000), %bb.1(0x7c000000)

%5:gpr64sp = PHI %4, %bb.0, %6, %bb.1
%7:gpr64 = PHI %2, %bb.0, %8, %bb.1
%9:fpr64 = LDRDui %1, 0
STRDui killed %9, %0, 0
%10:gpr64 = nsw SUBSXri %5, 1, 0, implicit-def $nzcv
%6:gpr64all = COPY %10
%8:gpr64all = SUBREG_TO_REG 0, %3, %subreg.sub_32
Bcc 1, %bb.1, implicit $nzcv
B %bb.2

bb.2:
successors: %bb.3(0x80000000)

bb.3:
successors: %bb.4(0x04000000), %bb.3(0x7c000000)

CBNZX %7, %bb.3
B %bb.4

bb.4:
successors: %bb.5(0x80000000)

%11:fpr64 = FMOVD0

bb.5:
successors: %bb.6(0x80000000)

%12:fpr64 = PHI %11, %bb.4, %13, %bb.6
%14:gpr64all = COPY $xzr
%15:gpr64all = COPY %14

bb.6:
successors: %bb.5(0x04000000), %bb.6(0x7c000000)

%16:gpr64common = PHI %15, %bb.5, %17, %bb.6
%18:fpr64 = PHI %12, %bb.5, %13, %bb.6
%19:gpr64common = UBFMXri %16, 61, 60
%20:fpr64 = LDRDui killed %19, 1
%13:fpr64 = nofpexcept FADDDrr %18, killed %20, implicit $fpcr
%21:gpr64 = ADDSXri %16, 1, 0, implicit-def $nzcv
%17:gpr64all = COPY %21
Bcc 2, %bb.5, implicit $nzcv
B %bb.6

...