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[MIPS] Define SubTargetFeature for i6500 cpu #132907

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Merged
merged 2 commits into from
Mar 27, 2025
Merged

[MIPS] Define SubTargetFeature for i6500 cpu #132907

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752aaec
[MIPS] Define SubTargetFeature for i6500 cpu
mgoudar Mar 25, 2025
7d59e51
[MIPS] remove extra line in the test case
mgoudar Mar 25, 2025
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5 changes: 5 additions & 0 deletions clang/test/CodeGen/Mips/subtarget-feature-test.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | FileCheck --allow-empty %s
// CHECK-NOT: {{.*}} is not a recognized feature for this target

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nit: no need for 2 newlines here

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thank you for the review. I have removed extra line.

// RUN: %clang --target=mips64-linux-gnu -mcpu=i6500 -o %t -c %s 2>&1 | FileCheck --allow-empty %s
// CHECK-NOT: {{.*}} is not a recognized feature for this target
8 changes: 6 additions & 2 deletions llvm/lib/Target/Mips/Mips.td
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Expand Up @@ -242,7 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
// same CPU architecture.
def ImplI6400
: SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
"MIPS I6400/I6500 Processors", [FeatureMips64r6]>;
"MIPS I6400 Processor", [FeatureMips64r6]>;

def ImplI6500
: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
"MIPS I6500 Processor", [FeatureMips64r6]>;

class Proc<string Name, list<SubtargetFeature> Features>
: ProcessorModel<Name, MipsGenericModel, Features>;
Expand All @@ -268,7 +272,7 @@ def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
def : ProcessorModel<"i6500", NoSchedModel, [ImplI6400]>;
def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;

def MipsAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsSubtarget.h
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Expand Up @@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};

enum class CPU { P5600, I6400 };
enum class CPU { P5600, I6400, I6500 };

// Used to avoid printing dsp warnings multiple times.
static bool DspWarningPrinted;
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