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[AMDGPU][GFX11] buffer_load_lds_{size} instructions do not exist #132916

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Merged
merged 1 commit into from
Mar 25, 2025
Merged

[AMDGPU][GFX11] buffer_load_lds_{size} instructions do not exist #132916

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6 changes: 0 additions & 6 deletions llvm/docs/AMDGPU/AMDGPUAsmGFX11.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -695,12 +695,6 @@ MUBUF
buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx11_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>`
buffer_load_i16 :ref:`vdst<amdgpu_synid_gfx11_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>`
buffer_load_i8 :ref:`vdst<amdgpu_synid_gfx11_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>`
buffer_load_lds_b32 :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_lds_format_x :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_lds_i16 :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_lds_i8 :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_lds_u16 :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_lds_u8 :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx11_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>`
buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx11_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>`
buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx11_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx11_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx11_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>`
Expand Down
44 changes: 0 additions & 44 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
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Expand Up @@ -588,25 +588,6 @@ multiclass MUBUF_Pseudo_Loads_Lds<string opName, ValueType load_vt = i32, Predic

}

multiclass MUBUF_Pseudo_Loads_LDSOpc<string opName,
ValueType load_vt = i32,
bit TiedDest = 0,
bit isLds = 0,
bit isLdsOpc = 1> {

defvar legal_load_vt = !if(!eq(!cast<string>(load_vt), !cast<string>(v3f16)), v4f16, load_vt);

def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, legal_load_vt, TiedDest, isLds, isLdsOpc>;
def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, legal_load_vt, TiedDest, isLds, isLdsOpc>;
def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, legal_load_vt, TiedDest, isLds, isLdsOpc>;
def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, legal_load_vt, TiedDest, isLds, isLdsOpc>;

def _VBUFFER_OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, legal_load_vt, TiedDest, isLds, isLdsOpc, 0, 1>;
def _VBUFFER_OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, legal_load_vt, TiedDest, isLds, isLdsOpc, 0, 1>;
def _VBUFFER_IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, legal_load_vt, TiedDest, isLds, isLdsOpc, 0, 1>;
def _VBUFFER_BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, legal_load_vt, TiedDest, isLds, isLdsOpc, 0, 1>;
}

class MUBUF_Store_Pseudo <string opName,
int addrKind,
ValueType store_vt,
Expand Down Expand Up @@ -972,25 +953,6 @@ defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads_Lds <
"buffer_load_dwordx4", v4i32, /*LDSPred=*/HasGFX950Insts
>;

defm BUFFER_LOAD_LDS_B32 : MUBUF_Pseudo_Loads_LDSOpc <
"buffer_load_lds_b32", i32
>;
defm BUFFER_LOAD_LDS_FORMAT_X : MUBUF_Pseudo_Loads_LDSOpc <
"buffer_load_lds_format_x", f32
>;
defm BUFFER_LOAD_LDS_I8 : MUBUF_Pseudo_Loads_LDSOpc <
"buffer_load_lds_i8", i32
>;
defm BUFFER_LOAD_LDS_I16 : MUBUF_Pseudo_Loads_LDSOpc <
"buffer_load_lds_i16", i32
>;
defm BUFFER_LOAD_LDS_U8 : MUBUF_Pseudo_Loads_LDSOpc <
"buffer_load_lds_u8", i32
>;
defm BUFFER_LOAD_LDS_U16 : MUBUF_Pseudo_Loads_LDSOpc <
"buffer_load_lds_u16", i32
>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_8_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_zext_8_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_16_global>;
Expand Down Expand Up @@ -2648,12 +2610,6 @@ defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_gfx11_gfx12<0x011, "buffe
defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_gfx11_gfx12<0x013, "buffer_load_i16">;
defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_gfx11_gfx12<0x010, "buffer_load_u8">;
defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_gfx11_gfx12<0x012, "buffer_load_u16">;
defm BUFFER_LOAD_LDS_B32 : MUBUF_Real_AllAddr_gfx11<0x031, 0>;
defm BUFFER_LOAD_LDS_FORMAT_X : MUBUF_Real_AllAddr_gfx11<0x032, 0>;
defm BUFFER_LOAD_LDS_I8 : MUBUF_Real_AllAddr_gfx11<0x02e, 0>;
defm BUFFER_LOAD_LDS_I16 : MUBUF_Real_AllAddr_gfx11<0x030, 0>;
defm BUFFER_LOAD_LDS_U8 : MUBUF_Real_AllAddr_gfx11<0x02d, 0>;
defm BUFFER_LOAD_LDS_U16 : MUBUF_Real_AllAddr_gfx11<0x02f, 0>;
defm BUFFER_STORE_BYTE : MUBUF_Real_AllAddr_gfx11_gfx12<0x018, "buffer_store_b8">;
defm BUFFER_STORE_SHORT : MUBUF_Real_AllAddr_gfx11_gfx12<0x019, "buffer_store_b16">;
defm BUFFER_STORE_DWORD : MUBUF_Real_AllAddr_gfx11_gfx12<0x01A, "buffer_store_b32">;
Expand Down
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