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[RISCV] Modify operand regclass in load store patterns #133071

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Merged
merged 2 commits into from
Mar 27, 2025
Merged

[RISCV] Modify operand regclass in load store patterns #133071

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96c2980
[RVIU] Add GPRMem to operand in load store patterns
svs-quic Mar 26, 2025
3755daa
Merge branch 'main' into loadstoremem
svs-quic Mar 27, 2025
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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1836,8 +1836,8 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
/// Loads

class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT>
: Pat<(vt (LoadOp (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
(Inst GPR:$rs1, simm12:$imm12)>;
: Pat<(vt (LoadOp (AddrRegImm (XLenVT GPRMem:$rs1), simm12:$imm12))),
(Inst GPRMem:$rs1, simm12:$imm12)>;

def : LdPat<sextloadi8, LB>;
def : LdPat<extloadi8, LBU>; // Prefer unsigned due to no c.lb in Zcb.
Expand All @@ -1851,9 +1851,9 @@ def : LdPat<zextloadi16, LHU>;

class StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
ValueType vt>
: Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPR:$rs1),
: Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPRMem:$rs1),
simm12:$imm12)),
(Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
(Inst StTy:$rs2, GPRMem:$rs1, simm12:$imm12)>;

def : StPat<truncstorei8, SB, GPR, XLenVT>;
def : StPat<truncstorei16, SH, GPR, XLenVT>;
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