Skip to content

[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). #133200

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Mar 27, 2025
Merged

[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). #133200

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 6 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoD.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -144,12 +144,14 @@ foreach Ext = DExts in {
"fcvt.wu.d">,
Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;

defm FCVT_D_W : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00000, Ext, Ext.PrimaryTy, GPR,
"fcvt.d.w">,
let mayRaiseFPException = 0 in
defm FCVT_D_W : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00000, Ext,
Ext.PrimaryTy, GPR, "fcvt.d.w">,
Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;

defm FCVT_D_WU : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00001, Ext, Ext.PrimaryTy, GPR,
"fcvt.d.wu">,
let mayRaiseFPException = 0 in
defm FCVT_D_WU : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00001, Ext,
Ext.PrimaryTy, GPR, "fcvt.d.wu">,
Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
} // foreach Ext = DExts

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_W [[COPY]], 0
; CHECK-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0
; CHECK-NEXT: $f10_d = COPY [[FCVT_D_W]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:gprb(s32) = COPY $x10
Expand All @@ -81,7 +81,7 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[FCVT_D_WU:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_WU [[COPY]], 0
; CHECK-NEXT: [[FCVT_D_WU:%[0-9]+]]:fpr64 = FCVT_D_WU [[COPY]], 0
; CHECK-NEXT: $f10_d = COPY [[FCVT_D_WU]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:gprb(s32) = COPY $x10
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/double-imm.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -123,9 +123,9 @@ define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind
; CHECK32D-LABEL: negzero_sel:
; CHECK32D: # %bb.0: # %entry
; CHECK32D-NEXT: slli a0, a0, 16
; CHECK32D-NEXT: fcvt.d.w fa5, zero
; CHECK32D-NEXT: beqz a0, .LBB4_2
; CHECK32D-NEXT: # %bb.1: # %entry
; CHECK32D-NEXT: fcvt.d.w fa5, zero
; CHECK32D-NEXT: fneg.d fa0, fa5
; CHECK32D-NEXT: .LBB4_2: # %entry
; CHECK32D-NEXT: ret
Expand All @@ -143,10 +143,10 @@ define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind
; CHECKRV32ZDINX-LABEL: negzero_sel:
; CHECKRV32ZDINX: # %bb.0: # %entry
; CHECKRV32ZDINX-NEXT: slli a0, a0, 16
; CHECKRV32ZDINX-NEXT: fcvt.d.w a4, zero
; CHECKRV32ZDINX-NEXT: beqz a0, .LBB4_2
; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry
; CHECKRV32ZDINX-NEXT: fneg.d a2, a4
; CHECKRV32ZDINX-NEXT: fcvt.d.w a0, zero
; CHECKRV32ZDINX-NEXT: fneg.d a2, a0
; CHECKRV32ZDINX-NEXT: j .LBB4_3
; CHECKRV32ZDINX-NEXT: .LBB4_2:
; CHECKRV32ZDINX-NEXT: mv a3, a2
Expand Down
9 changes: 5 additions & 4 deletions llvm/test/CodeGen/RISCV/frm-dependency.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -87,16 +87,17 @@ define double @fcvt_d_w(i32 %a) nounwind {
; RV32IF-NEXT: liveins: $x10
; RV32IF-NEXT: {{ $}}
; RV32IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV32IF-NEXT: %1:fpr64 = nofpexcept FCVT_D_W [[COPY]]
; RV32IF-NEXT: $f10_d = COPY %1
; RV32IF-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0
; RV32IF-NEXT: $f10_d = COPY [[FCVT_D_W]]
; RV32IF-NEXT: PseudoRET implicit $f10_d
;
; RV64IF-LABEL: name: fcvt_d_w
; RV64IF: bb.0 (%ir-block.0):
; RV64IF-NEXT: liveins: $x10
; RV64IF-NEXT: {{ $}}
; RV64IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV64IF-NEXT: %1:fpr64 = nofpexcept FCVT_D_W [[COPY]]
; RV64IF-NEXT: $f10_d = COPY %1
; RV64IF-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0
; RV64IF-NEXT: $f10_d = COPY [[FCVT_D_W]]
; RV64IF-NEXT: PseudoRET implicit $f10_d
%1 = sitofp i32 %a to double
ret double %1
Expand Down