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[RISCV] Reverse the order of Base and Offset in Core-V RegReg operand. #133209

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Merged
merged 1 commit into from
Mar 27, 2025
Merged

[RISCV] Reverse the order of Base and Offset in Core-V RegReg operand. #133209

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14 changes: 7 additions & 7 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2768,9 +2768,9 @@ ParseStatus RISCVAsmParser::parseRegReg(OperandVector &Operands) {
if (getLexer().getKind() != AsmToken::Identifier)
return ParseStatus::NoMatch;

StringRef RegName = getLexer().getTok().getIdentifier();
MCRegister Reg = matchRegisterNameHelper(RegName);
if (!Reg)
StringRef OffsetRegName = getLexer().getTok().getIdentifier();
MCRegister OffsetReg = matchRegisterNameHelper(OffsetRegName);
if (!OffsetReg)
return Error(getLoc(), "invalid register");
getLexer().Lex();

Expand All @@ -2780,16 +2780,16 @@ ParseStatus RISCVAsmParser::parseRegReg(OperandVector &Operands) {
if (getLexer().getKind() != AsmToken::Identifier)
return Error(getLoc(), "expected register");

StringRef Reg2Name = getLexer().getTok().getIdentifier();
MCRegister Reg2 = matchRegisterNameHelper(Reg2Name);
if (!Reg2)
StringRef BaseRegName = getLexer().getTok().getIdentifier();
MCRegister BaseReg = matchRegisterNameHelper(BaseRegName);
if (!BaseReg)
return Error(getLoc(), "invalid register");
getLexer().Lex();

if (parseToken(AsmToken::RParen, "expected ')'"))
return ParseStatus::Failure;

Operands.push_back(RISCVOperand::createRegReg(Reg, Reg2, getLoc()));
Operands.push_back(RISCVOperand::createRegReg(BaseReg, OffsetReg, getLoc()));

return ParseStatus::Success;
}
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12 changes: 6 additions & 6 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
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Expand Up @@ -262,15 +262,15 @@ void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,

void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNo);
const MCOperand &OffsetMO = MI->getOperand(OpNo + 1);

assert(MO.isReg() && "printRegReg can only print register operands");
printRegName(O, MO.getReg());
assert(OffsetMO.isReg() && "printRegReg can only print register operands");
printRegName(O, OffsetMO.getReg());

O << "(";
const MCOperand &MO1 = MI->getOperand(OpNo + 1);
assert(MO1.isReg() && "printRegReg can only print register operands");
printRegName(O, MO1.getReg());
const MCOperand &BaseMO = MI->getOperand(OpNo);
assert(BaseMO.isReg() && "printRegReg can only print register operands");
printRegName(O, BaseMO.getReg());
O << ")";
}

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Expand Up @@ -2853,8 +2853,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegReg(SDValue Addr, SDValue &Base,
if (isa<ConstantSDNode>(Addr.getOperand(1)))
return false;

Base = Addr.getOperand(1);
Offset = Addr.getOperand(0);
Base = Addr.getOperand(0);
Offset = Addr.getOperand(1);
return true;
}

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6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
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Expand Up @@ -25,7 +25,7 @@ def CVrr : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrRegReg",[]> {
let ParserMatchClass = CVrrAsmOperand;
let PrintMethod = "printRegReg";
let MIOperandInfo = (ops GPR:$offset, GPR:$base);
let MIOperandInfo = (ops GPR:$base, GPR:$offset);
}

def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
Expand Down Expand Up @@ -287,7 +287,7 @@ class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>

class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
(ins (CVrr $rs2, $rs1):$addr),
(ins (CVrr $rs1, $rs2):$addr),
opcodestr, "$rd, $addr">;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0

Expand Down Expand Up @@ -317,7 +317,7 @@ class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, string opcodestr>


class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
: RVInst<(outs), (ins GPR:$rs2, (CVrr $rs3, $rs1):$addr), opcodestr,
: RVInst<(outs), (ins GPR:$rs2, (CVrr $rs1, $rs3):$addr), opcodestr,
"$rs2, $addr", [], InstFormatOther> {
bits<5> rs1;
bits<5> rs2;
Expand Down