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[AMDGPU] Add subtarget feature for v_lshl_add_u64. NFC. #133723

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Merged
merged 2 commits into from
Mar 31, 2025
Merged

[AMDGPU] Add subtarget feature for v_lshl_add_u64. NFC. #133723

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c4f3443
[AMDGPU] Add subtarget feature for v_lshl_add_u64. NFC.
jayfoad Mar 31, 2025
ed4fd8a
Add inst suffix
jayfoad Mar 31, 2025
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10 changes: 9 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPU.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1269,6 +1269,10 @@ def FeatureDynamicVGPRBlockSize32 : SubtargetFeature<"dynamic-vgpr-block-size-32
"Use a block size of 32 for dynamic VGPR allocation (default is 16)"
>;

def FeatureLshlAddU64Inst
: SubtargetFeature<"lshl-add-u64-inst", "HasLshlAddU64Inst", "true",
"Has v_lshl_add_u64 instruction">;

// Dummy feature used to disable assembler instructions.
def FeatureDisable : SubtargetFeature<"",
"FeatureDisable","true",
Expand Down Expand Up @@ -1622,7 +1626,8 @@ def FeatureISAVersion9_4_Common : FeatureSet<
FeatureAtomicFMinFMaxF64FlatInsts,
FeatureAgentScopeFineGrainedRemoteMemoryAtomics,
FeatureMemoryAtomicFAddF32DenormalSupport,
FeatureFlatBufferGlobalAtomicFaddF64Inst
FeatureFlatBufferGlobalAtomicFaddF64Inst,
FeatureLshlAddU64Inst,
]>;

def FeatureISAVersion9_5_Common : FeatureSet<
Expand Down Expand Up @@ -2554,6 +2559,9 @@ def HasXF32Insts : Predicate<"Subtarget->hasXF32Insts()">,
def HasAshrPkInsts : Predicate<"Subtarget->hasAshrPkInsts()">,
AssemblerPredicate<(all_of FeatureAshrPkInsts)>;

def HasLshlAddU64Inst : Predicate<"Subtarget->hasLshlAddU64Inst()">,
AssemblerPredicate<(all_of FeatureLshlAddU64Inst)>;

// Include AMDGPU TD files
include "SISchedule.td"
include "GCNProcessors.td"
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/GCNSubtarget.h
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Expand Up @@ -257,6 +257,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasMinimum3Maximum3F32 = false;
bool HasMinimum3Maximum3F16 = false;
bool HasMinimum3Maximum3PKF16 = false;
bool HasLshlAddU64Inst = false;

bool RequiresCOV6 = false;

Expand Down Expand Up @@ -1140,7 +1141,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,

bool hasMovB64() const { return GFX940Insts; }

bool hasLshlAddB64() const { return GFX940Insts; }
bool hasLshlAddU64Inst() const { return HasLshlAddU64Inst; }

bool enableSIScheduler() const {
return EnableSIScheduler;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -5246,7 +5246,7 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineOperand &Src0 = MI.getOperand(1);
MachineOperand &Src1 = MI.getOperand(2);

if (IsAdd && ST.hasLshlAddB64()) {
if (IsAdd && ST.hasLshlAddU64Inst()) {
auto Add = BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_LSHL_ADD_U64_e64),
Dest.getReg())
.add(Src0)
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Expand Up @@ -679,7 +679,7 @@ defm V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32

// V_LSHL_ADD_U64: D0.u64 = (S0.u64 << S1.u[2:0]) + S2.u64
// src0 is shifted left by 0-4 (use “0” to get ADD_U64).
let SubtargetPredicate = isGFX940Plus in
let SubtargetPredicate = HasLshlAddU64Inst in
defm V_LSHL_ADD_U64 : VOP3Inst <"v_lshl_add_u64", VOP3_Profile<VOP_I64_I64_I32_I64>>;

let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0,
Expand Down
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