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[LLVM][CodeGen][SVE] Prefer NEON instructions when zeroing Z registers. #133929

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Apr 3, 2025
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[LLVM][CodeGen][SVE] Prefer NEON instructions when zeroing Z registers. #133929

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19 changes: 19 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -7731,6 +7731,7 @@ def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128,
"movi", ".2d",
[(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;

let Predicates = [HasNEON] in {
def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
Comment on lines +7734 to 7735
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Presumably, these other fixed-vector patterns were already not reachable in streaming-mode?

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Yes, the fixed length spat/build vector would have been legalised so that it cannot get this far. I figured since I was protecting the code for scalable vector types I may as well just protect the whole related block.

def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
Expand All @@ -7740,6 +7741,23 @@ def : Pat<(v4f32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
def : Pat<(v8f16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
def : Pat<(v8bf16 immAllZerosV), (MOVIv2d_ns (i32 0))>;

// Prefer NEON instructions when zeroing ZPRs because they are potentially zero-latency.
let AddedComplexity = 5 in {
def : Pat<(nxv2i64 (splat_vector (i64 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv4i32 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv8i16 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv16i8 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv2f64 (splat_vector (f64 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv2f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv4f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv2f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv4f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv8f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv2bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv4bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
def : Pat<(nxv8bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;
}

def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
Expand All @@ -7760,6 +7778,7 @@ def : Pat<(v1i64 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
def : Pat<(v2i32 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
def : Pat<(v4i16 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
def : Pat<(v8i8 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
}

// EDIT per word & halfword: 2s, 4h, 4s, & 8h
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
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Expand Up @@ -50,10 +50,10 @@ entry:
define <vscale x 4 x double> @mul_add_mull(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, <vscale x 4 x double> %d) {
; CHECK-LABEL: mul_add_mull:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: mov z26.d, #0 // =0x0
; CHECK-NEXT: mov z27.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z24.d, p0/m, z2.d, z0.d, #0
; CHECK-NEXT: fcmla z25.d, p0/m, z3.d, z1.d, #0
Expand Down Expand Up @@ -101,10 +101,10 @@ entry:
define <vscale x 4 x double> @mul_sub_mull(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, <vscale x 4 x double> %d) {
; CHECK-LABEL: mul_sub_mull:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: mov z26.d, #0 // =0x0
; CHECK-NEXT: mov z27.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z24.d, p0/m, z2.d, z0.d, #0
; CHECK-NEXT: fcmla z25.d, p0/m, z3.d, z1.d, #0
Expand Down Expand Up @@ -152,10 +152,10 @@ entry:
define <vscale x 4 x double> @mul_conj_mull(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, <vscale x 4 x double> %d) {
; CHECK-LABEL: mul_conj_mull:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: mov z26.d, #0 // =0x0
; CHECK-NEXT: mov z27.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z24.d, p0/m, z2.d, z0.d, #0
; CHECK-NEXT: fcmla z25.d, p0/m, z3.d, z1.d, #0
Expand Down Expand Up @@ -204,7 +204,7 @@ define <vscale x 4 x double> @mul_add_rot_mull(<vscale x 4 x double> %a, <vscale
; CHECK-LABEL: mul_add_rot_mull:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uzp2 z24.d, z4.d, z5.d
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: uzp1 z4.d, z4.d, z5.d
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z26.d, z24.d
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
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Expand Up @@ -41,8 +41,8 @@ entry:
define <vscale x 4 x double> @mul_add_mull(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, <vscale x 4 x double> %d) {
; CHECK-LABEL: mul_add_mull:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z25.d, p0/m, z6.d, z4.d, #0
; CHECK-NEXT: fcmla z24.d, p0/m, z7.d, z5.d, #0
Expand Down Expand Up @@ -90,8 +90,8 @@ entry:
define <vscale x 4 x double> @mul_sub_mull(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, <vscale x 4 x double> %d) {
; CHECK-LABEL: mul_sub_mull:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z25.d, p0/m, z6.d, z4.d, #270
; CHECK-NEXT: fcmla z24.d, p0/m, z7.d, z5.d, #270
Expand Down Expand Up @@ -139,8 +139,8 @@ entry:
define <vscale x 4 x double> @mul_conj_mull(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, <vscale x 4 x double> %d) {
; CHECK-LABEL: mul_conj_mull:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z25.d, p0/m, z0.d, z2.d, #0
; CHECK-NEXT: fcmla z24.d, p0/m, z1.d, z3.d, #0
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
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Expand Up @@ -46,7 +46,7 @@ entry:
define <vscale x 8 x half> @complex_mul_v8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
; CHECK-LABEL: complex_mul_v8f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: fcmla z2.h, p0/m, z1.h, z0.h, #0
; CHECK-NEXT: fcmla z2.h, p0/m, z1.h, z0.h, #90
Expand All @@ -72,8 +72,8 @@ entry:
define <vscale x 16 x half> @complex_mul_v16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b) {
; CHECK-LABEL: complex_mul_v16f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z4.h, #0 // =0x0
; CHECK-NEXT: mov z5.h, #0 // =0x0
; CHECK-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEXT: movi v5.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: fcmla z5.h, p0/m, z2.h, z0.h, #0
; CHECK-NEXT: fcmla z4.h, p0/m, z3.h, z1.h, #0
Expand Down Expand Up @@ -103,10 +103,10 @@ entry:
define <vscale x 32 x half> @complex_mul_v32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b) {
; CHECK-LABEL: complex_mul_v32f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.h, #0 // =0x0
; CHECK-NEXT: mov z25.h, #0 // =0x0
; CHECK-NEXT: mov z26.h, #0 // =0x0
; CHECK-NEXT: mov z27.h, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: fcmla z24.h, p0/m, z4.h, z0.h, #0
; CHECK-NEXT: fcmla z25.h, p0/m, z5.h, z1.h, #0
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
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Expand Up @@ -7,7 +7,7 @@ target triple = "aarch64"
define <vscale x 4 x float> @complex_mul_v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
; CHECK-LABEL: complex_mul_v4f32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z2.s, #0 // =0x0
; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: fcmla z2.s, p0/m, z1.s, z0.s, #0
; CHECK-NEXT: fcmla z2.s, p0/m, z1.s, z0.s, #90
Expand All @@ -34,8 +34,8 @@ entry:
define <vscale x 8 x float> @complex_mul_v8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b) {
; CHECK-LABEL: complex_mul_v8f32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z4.s, #0 // =0x0
; CHECK-NEXT: mov z5.s, #0 // =0x0
; CHECK-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEXT: movi v5.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: fcmla z5.s, p0/m, z2.s, z0.s, #0
; CHECK-NEXT: fcmla z4.s, p0/m, z3.s, z1.s, #0
Expand Down Expand Up @@ -65,10 +65,10 @@ entry:
define <vscale x 16 x float> @complex_mul_v16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b) {
; CHECK-LABEL: complex_mul_v16f32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.s, #0 // =0x0
; CHECK-NEXT: mov z25.s, #0 // =0x0
; CHECK-NEXT: mov z26.s, #0 // =0x0
; CHECK-NEXT: mov z27.s, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: fcmla z24.s, p0/m, z4.s, z0.s, #0
; CHECK-NEXT: fcmla z25.s, p0/m, z5.s, z1.s, #0
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
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Expand Up @@ -7,7 +7,7 @@ target triple = "aarch64"
define <vscale x 2 x double> @complex_mul_v2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
; CHECK-LABEL: complex_mul_v2f64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z2.d, #0 // =0x0
; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z2.d, p0/m, z1.d, z0.d, #0
; CHECK-NEXT: fcmla z2.d, p0/m, z1.d, z0.d, #90
Expand All @@ -34,8 +34,8 @@ entry:
define <vscale x 4 x double> @complex_mul_v4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b) {
; CHECK-LABEL: complex_mul_v4f64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z4.d, #0 // =0x0
; CHECK-NEXT: mov z5.d, #0 // =0x0
; CHECK-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEXT: movi v5.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z5.d, p0/m, z2.d, z0.d, #0
; CHECK-NEXT: fcmla z4.d, p0/m, z3.d, z1.d, #0
Expand Down Expand Up @@ -65,10 +65,10 @@ entry:
define <vscale x 8 x double> @complex_mul_v8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b) {
; CHECK-LABEL: complex_mul_v8f64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: mov z26.d, #0 // =0x0
; CHECK-NEXT: mov z27.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmla z24.d, p0/m, z4.d, z0.d, #0
; CHECK-NEXT: fcmla z25.d, p0/m, z5.d, z1.d, #0
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
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Expand Up @@ -46,7 +46,7 @@ entry:
define <vscale x 8 x i16> @complex_mul_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: complex_mul_v8i16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: cmla z2.h, z1.h, z0.h, #0
; CHECK-NEXT: cmla z2.h, z1.h, z0.h, #90
; CHECK-NEXT: mov z0.d, z2.d
Expand All @@ -71,8 +71,8 @@ entry:
define <vscale x 16 x i16> @complex_mul_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
; CHECK-LABEL: complex_mul_v16i16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z4.h, #0 // =0x0
; CHECK-NEXT: mov z5.h, #0 // =0x0
; CHECK-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEXT: movi v5.2d, #0000000000000000
; CHECK-NEXT: cmla z5.h, z2.h, z0.h, #0
; CHECK-NEXT: cmla z4.h, z3.h, z1.h, #0
; CHECK-NEXT: cmla z5.h, z2.h, z0.h, #90
Expand Down Expand Up @@ -101,10 +101,10 @@ entry:
define <vscale x 32 x i16> @complex_mul_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
; CHECK-LABEL: complex_mul_v32i16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.h, #0 // =0x0
; CHECK-NEXT: mov z25.h, #0 // =0x0
; CHECK-NEXT: mov z26.h, #0 // =0x0
; CHECK-NEXT: mov z27.h, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: cmla z24.h, z4.h, z0.h, #0
; CHECK-NEXT: cmla z25.h, z5.h, z1.h, #0
; CHECK-NEXT: cmla z27.h, z6.h, z2.h, #0
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll
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Expand Up @@ -7,7 +7,7 @@ target triple = "aarch64"
define <vscale x 4 x i32> @complex_mul_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: complex_mul_v4i32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z2.s, #0 // =0x0
; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: cmla z2.s, z1.s, z0.s, #0
; CHECK-NEXT: cmla z2.s, z1.s, z0.s, #90
; CHECK-NEXT: mov z0.d, z2.d
Expand All @@ -33,8 +33,8 @@ entry:
define <vscale x 8 x i32> @complex_mul_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
; CHECK-LABEL: complex_mul_v8i32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z4.s, #0 // =0x0
; CHECK-NEXT: mov z5.s, #0 // =0x0
; CHECK-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEXT: movi v5.2d, #0000000000000000
; CHECK-NEXT: cmla z5.s, z2.s, z0.s, #0
; CHECK-NEXT: cmla z4.s, z3.s, z1.s, #0
; CHECK-NEXT: cmla z5.s, z2.s, z0.s, #90
Expand Down Expand Up @@ -63,10 +63,10 @@ entry:
define <vscale x 16 x i32> @complex_mul_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
; CHECK-LABEL: complex_mul_v16i32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.s, #0 // =0x0
; CHECK-NEXT: mov z25.s, #0 // =0x0
; CHECK-NEXT: mov z26.s, #0 // =0x0
; CHECK-NEXT: mov z27.s, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: cmla z24.s, z4.s, z0.s, #0
; CHECK-NEXT: cmla z25.s, z5.s, z1.s, #0
; CHECK-NEXT: cmla z27.s, z6.s, z2.s, #0
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll
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Expand Up @@ -7,7 +7,7 @@ target triple = "aarch64"
define <vscale x 2 x i64> @complex_mul_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: complex_mul_v2i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z2.d, #0 // =0x0
; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: cmla z2.d, z1.d, z0.d, #0
; CHECK-NEXT: cmla z2.d, z1.d, z0.d, #90
; CHECK-NEXT: mov z0.d, z2.d
Expand All @@ -33,8 +33,8 @@ entry:
define <vscale x 4 x i64> @complex_mul_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
; CHECK-LABEL: complex_mul_v4i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z4.d, #0 // =0x0
; CHECK-NEXT: mov z5.d, #0 // =0x0
; CHECK-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEXT: movi v5.2d, #0000000000000000
; CHECK-NEXT: cmla z5.d, z2.d, z0.d, #0
; CHECK-NEXT: cmla z4.d, z3.d, z1.d, #0
; CHECK-NEXT: cmla z5.d, z2.d, z0.d, #90
Expand Down Expand Up @@ -63,10 +63,10 @@ entry:
define <vscale x 8 x i64> @complex_mul_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
; CHECK-LABEL: complex_mul_v8i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: mov z26.d, #0 // =0x0
; CHECK-NEXT: mov z27.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: cmla z24.d, z4.d, z0.d, #0
; CHECK-NEXT: cmla z25.d, z5.d, z1.d, #0
; CHECK-NEXT: cmla z27.d, z6.d, z2.d, #0
Expand Down Expand Up @@ -101,10 +101,10 @@ entry:
define <vscale x 8 x i64> @complex_minus_mul_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
; CHECK-LABEL: complex_minus_mul_v8i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z24.d, #0 // =0x0
; CHECK-NEXT: mov z25.d, #0 // =0x0
; CHECK-NEXT: mov z26.d, #0 // =0x0
; CHECK-NEXT: mov z27.d, #0 // =0x0
; CHECK-NEXT: movi v24.2d, #0000000000000000
; CHECK-NEXT: movi v25.2d, #0000000000000000
; CHECK-NEXT: movi v26.2d, #0000000000000000
; CHECK-NEXT: movi v27.2d, #0000000000000000
; CHECK-NEXT: cmla z24.d, z4.d, z0.d, #270
; CHECK-NEXT: cmla z25.d, z5.d, z1.d, #270
; CHECK-NEXT: cmla z27.d, z6.d, z2.d, #270
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
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Expand Up @@ -14,7 +14,7 @@ target triple = "aarch64"
define %"class.std::complex" @complex_mul_v2f64(ptr %a, ptr %b) {
; CHECK-LABEL: complex_mul_v2f64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z1.d, #0 // =0x0
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, #100 // =0x64
; CHECK-NEXT: cntd x9
; CHECK-NEXT: whilelo p1.d, xzr, x8
Expand Down Expand Up @@ -111,7 +111,7 @@ exit.block: ; preds = %vector.body
define %"class.std::complex" @complex_mul_predicated_v2f64(ptr %a, ptr %b, ptr %cond) {
; CHECK-LABEL: complex_mul_predicated_v2f64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z1.d, #0 // =0x0
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: cntd x9
; CHECK-NEXT: mov w11, #100 // =0x64
; CHECK-NEXT: neg x10, x9
Expand Down Expand Up @@ -213,7 +213,7 @@ exit.block: ; preds = %vector.body
define %"class.std::complex" @complex_mul_predicated_x2_v2f64(ptr %a, ptr %b, ptr %cond) {
; CHECK-LABEL: complex_mul_predicated_x2_v2f64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z1.d, #0 // =0x0
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, #100 // =0x64
; CHECK-NEXT: cntd x9
; CHECK-NEXT: whilelo p1.d, xzr, x8
Expand Down
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