[RISCV] Improve error for using x18-x27 in a register list with RVE.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -2577,7 +2577,7 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
   if (parseToken(AsmToken::LCurly, "register list must start with '{'"))
     return ParseStatus::Failure;
 
-  bool IsEABI = isRVE();
+  bool IsRVE = isRVE();
 
   if (getLexer().isNot(AsmToken::Identifier))
     return Error(getLoc(), "register list must start from 'ra' or 'x1'");
@@ -2617,46 +2617,41 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
   // parse case like -s1
   if (parseOptionalToken(AsmToken::Minus)) {
     StringRef EndName = getLexer().getTok().getIdentifier();
-    // FIXME: the register mapping and checks of EABI is wrong
+    // FIXME: the register mapping and checks of RVE is wrong
     RegEnd = matchRegisterNameHelper(EndName);
     if (!(RegEnd == RISCV::X9 ||
           (RegEnd >= RISCV::X18 && RegEnd <= RISCV::X27)))
       return Error(getLoc(), "invalid register");
-    if (IsEABI && RegEnd != RISCV::X9)
-      return Error(getLoc(), "contiguous register list of EABI can only be "
-                             "'s0-s1' or 'x8-x9' pair");
     getLexer().Lex();
   }
 
-  if (!IsEABI) {
-    // parse extra part like ', x18[-x20]' for XRegList
-    if (parseOptionalToken(AsmToken::Comma)) {
-      if (RegEnd != RISCV::X9)
-        return Error(
-            getLoc(),
-            "first contiguous registers pair of register list must be 'x8-x9'");
+  // parse extra part like ', x18[-x20]' for XRegList
+  if (parseOptionalToken(AsmToken::Comma)) {
+    if (RegEnd != RISCV::X9)
+      return Error(
+          getLoc(),
+          "first contiguous registers pair of register list must be 'x8-x9'");
 
-      // parse ', x18' for extra part
-      if (getLexer().isNot(AsmToken::Identifier))
+    // parse ', x18' for extra part
+    if (getLexer().isNot(AsmToken::Identifier) || IsRVE)
+      return Error(getLoc(), "invalid register");
+    StringRef EndName = getLexer().getTok().getIdentifier();
+    RegEnd = MatchRegisterName(EndName);
+    if (RegEnd != RISCV::X18)
+      return Error(getLoc(),
+                   "second contiguous registers pair of register list "
+                   "must start from 'x18'");
+    getLexer().Lex();
+
+    // parse '-x20' for extra part
+    if (parseOptionalToken(AsmToken::Minus)) {
+      if (getLexer().isNot(AsmToken::Identifier) || IsRVE)
         return Error(getLoc(), "invalid register");
-      StringRef EndName = getLexer().getTok().getIdentifier();
+      EndName = getLexer().getTok().getIdentifier();
       RegEnd = MatchRegisterName(EndName);
-      if (RegEnd != RISCV::X18)
-        return Error(getLoc(),
-                     "second contiguous registers pair of register list "
-                     "must start from 'x18'");
+      if (!(RegEnd >= RISCV::X19 && RegEnd <= RISCV::X27))
+        return Error(getLoc(), "invalid register");
       getLexer().Lex();
-
-      // parse '-x20' for extra part
-      if (parseOptionalToken(AsmToken::Minus)) {
-        if (getLexer().isNot(AsmToken::Identifier))
-          return Error(getLoc(), "invalid register");
-        EndName = getLexer().getTok().getIdentifier();
-        RegEnd = MatchRegisterName(EndName);
-        if (!(RegEnd >= RISCV::X19 && RegEnd <= RISCV::X27))
-          return Error(getLoc(), "invalid register");
-        getLexer().Lex();
-      }
     }
   }
 
@@ -2667,7 +2662,7 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
   if (parseToken(AsmToken::RCurly, "register list must end with '}'"))
     return ParseStatus::Failure;
 
-  auto Encode = RISCVZC::encodeRlist(RegEnd, IsEABI);
+  auto Encode = RISCVZC::encodeRlist(RegEnd, IsRVE);
   assert(Encode != RISCVZC::INVALID_RLIST);
   if (MustIncludeS0)
     assert(Encode != RISCVZC::RA);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -603,8 +603,8 @@ enum RLISTENCODE {
   INVALID_RLIST,
 };
 
-inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
-  assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
+inline unsigned encodeRlist(MCRegister EndReg, bool IsRVE = false) {
+  assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
   switch (EndReg) {
   case RISCV::X1:
     return RLISTENCODE::RA;

llvm/test/MC/RISCV/rv32e-xqccmp-invalid.s

@@ -14,8 +14,11 @@ qc.cm.push {ra,s0-s2}, -16
 # CHECK: :[[@LINE+1]]:21: error: invalid register
 qc.cm.popret {ra,s0-s2}, 16
 # CHECK-DIS: ba72 <unknown>
-# CHECK: :[[@LINE+1]]:21: error: register list must end with '}'
+# CHECK: :[[@LINE+1]]:23: error: invalid register
 qc.cm.pop {x1, x8-x9, x18}, 16
 # CHECK-DIS: b972 <unknown>
-# CHECK: :[[@LINE+1]]:24: error: register list must end with '}'
+# CHECK: :[[@LINE+1]]:26: error: invalid register
 qc.cm.pushfp {x1, x8-x9, x18}, -16
+# CHECK-DIS: b972 <unknown>
+# CHECK: :[[@LINE+1]]:22: error: invalid register
+qc.cm.pushfp {ra, s0-s2}, -16

llvm/test/MC/RISCV/rv32e-zcmp-invalid.s

@@ -14,5 +14,8 @@ cm.push {ra,s0-s2}, -16
 # CHECK: :[[@LINE+1]]:18: error: invalid register
 cm.popret {ra,s0-s2}, 16
 # CHECK-DIS: ba72 <unknown>
-# CHECK: :[[@LINE+1]]:18: error: register list must end with '}'
+# CHECK: :[[@LINE+1]]:20: error: invalid register
 cm.pop {x1, x8-x9, x18}, 16
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:16: error: invalid register
+cm.pop {ra, s0-s2}, 16

llvm/test/MC/RISCV/rv64e-xqccmp-invalid.s

@@ -14,8 +14,11 @@ qc.cm.push {ra,s0-s2}, -32
 # CHECK: :[[@LINE+1]]:21: error: invalid register
 qc.cm.popret {ra,s0-s2}, 32
 # CHECK-DIS: ba72 <unknown>
-# CHECK: :[[@LINE+1]]:21: error: register list must end with '}'
+# CHECK: :[[@LINE+1]]:23: error: invalid register
 qc.cm.pop {x1, x8-x9, x18}, 32
 # CHECK-DIS: b972 <unknown>
-# CHECK: :[[@LINE+1]]:24: error: register list must end with '}'
+# CHECK: :[[@LINE+1]]:26: error: invalid register
 qc.cm.pushfp {x1, x8-x9, x18}, -32
+# CHECK-DIS: b972 <unknown>
+# CHECK: :[[@LINE+1]]:22: error: invalid register
+qc.cm.pushfp {ra, s0-s2}, -32

llvm/test/MC/RISCV/rv64e-zcmp-invalid.s

@@ -14,5 +14,8 @@ cm.push {ra,s0-s2}, -32
 # CHECK: :[[@LINE+1]]:18: error: invalid register
 cm.popret {ra,s0-s2}, 32
 # CHECK-DIS: ba72 <unknown>
-# CHECK: :[[@LINE+1]]:18: error: register list must end with '}'
+# CHECK: :[[@LINE+1]]:20: error: invalid register
 cm.pop {x1, x8-x9, x18}, 32
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:16: error: invalid register
+cm.pop {ra, s0-s2}, 32