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[RISCV] Just reporting an error shouldn't generate a crash diagnostic #134040

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Merged
merged 4 commits into from
Apr 15, 2025
Merged

[RISCV] Just reporting an error shouldn't generate a crash diagnostic #134040

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a394bf5
Just reporting an error so report_fatal_error won't GenCrashDiag
paulhuggett Apr 2, 2025
3ce1899
Update target-abi-invalid so that it no longer expects crashes
paulhuggett Apr 2, 2025
6cad02c
Tweak a comment so that it makes more sense.
paulhuggett Apr 2, 2025
33c8f67
Ad "gen_crash_diag=" comments.
paulhuggett Apr 15, 2025
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18 changes: 13 additions & 5 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,14 @@ namespace RISCV {
#include "RISCVGenSearchableTables.inc"
} // namespace RISCV

// Report an error but don't ask the user to report a bug.
[[noreturn]] static void reportError(const char *Reason) {
report_fatal_error(Reason, /*gen_crash_diag=*/false);
}
[[noreturn]] static void reportError(Error Err) {
report_fatal_error(std::move(Err), /*gen_crash_diag=*/false);
}

namespace RISCVABI {
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
StringRef ABIName) {
Expand Down Expand Up @@ -87,15 +95,15 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
(TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
FeatureBits[RISCV::FeatureStdExtD])
report_fatal_error("ILP32E cannot be used with the D ISA extension");
reportError("ILP32E cannot be used with the D ISA extension");

if (TargetABI != ABI_Unknown)
return TargetABI;

// If no explicit ABI is given, try to compute the default ABI.
auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
if (!ISAInfo)
report_fatal_error(ISAInfo.takeError());
reportError(ISAInfo.takeError());
return getTargetABI((*ISAInfo)->computeDefaultABI());
}

Expand Down Expand Up @@ -127,12 +135,12 @@ namespace RISCVFeatures {

void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
report_fatal_error("RV64 target requires an RV64 CPU");
reportError("RV64 target requires an RV64 CPU");
if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
report_fatal_error("RV32 target requires an RV32 CPU");
reportError("RV32 target requires an RV32 CPU");
if (FeatureBits[RISCV::Feature32Bit] &&
FeatureBits[RISCV::Feature64Bit])
report_fatal_error("RV32 and RV64 can't be combined");
reportError("RV32 and RV64 can't be combined");
}

llvm::Expected<std::unique_ptr<RISCVISAInfo>>
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/MC/RISCV/target-abi-invalid.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
# RUN: | FileCheck -check-prefix=RV32E-LP64 %s
# RUN: llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32EF-LP64F %s
# RUN: not --crash llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
# RUN: not llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32EFD-LP64D %s
# RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64e %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32E-LP64E %s
Expand Down Expand Up @@ -70,9 +70,9 @@
# RUN: | FileCheck -check-prefix=RV32EF-ILP32F %s
# RUN: llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi ilp32f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32EF-ILP32F %s
# RUN: not --crash llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32f < %s 2>&1 \
# RUN: not llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32EFD-ILP32F %s
# RUN: not --crash llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32d < %s 2>&1 \
# RUN: not llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32d < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32EFD-ILP32D %s

# RV32E-ILP32: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
Expand Down
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