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PowerPC32:PIC: Update to bcl to fix branch prediction mis-predict issue #134140

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Merged
merged 4 commits into from
Apr 7, 2025
Merged

PowerPC32:PIC: Update to bcl to fix branch prediction mis-predict issue #134140

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819cfd5
PowerPC32:PIC: Update to bcl to fix branch prediction mis-predict issue
lei137 Apr 2, 2025
823ddd4
run clang-format
lei137 Apr 2, 2025
94ca9b9
Remove update for PPC::MoveGOTtoLR pseudo
lei137 Apr 4, 2025
b1e2b2a
restore ck for conversion of bl .+4
lei137 Apr 4, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -967,9 +967,9 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
// L1$pb:
MCSymbol *PICBase = MF->getPICBaseSymbol();

// Emit the 'bl'.
// Emit 'bcl 20,31,.+4' so the link stack is not corrupted.
EmitToStreamer(*OutStreamer,
MCInstBuilder(PPC::BL)
MCInstBuilder(PPC::BCLalways)
// FIXME: We would like an efficient form for this, so we
// don't have to do a lot of extra uniquing.
.addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/mcm-5.ll
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Expand Up @@ -51,7 +51,7 @@ sw.epilog: ; preds = %sw.bb3, %sw.default
ret i32 %5
}
; CHECK-LABEL: test_jump_table:
; CHECK-NOT: bl .L0$pb
; CHECK-NOT: bcl 20, 31, .L0$pb
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Silly question - the .L0$pb is supposed to evaluate to .+4, I assume?

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Yes. If you look at the LARGE code gen, .L0$pb: is the instruction right after bcl so it's +4 from the bcl instruction.

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Oh! Yes, good point. That makes sense. Thank you for pointing that out!


; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
Expand All @@ -64,7 +64,7 @@ sw.epilog: ; preds = %sw.bb3, %sw.default
; CHECK-NEXT: .long .LBB0_{{[0-9]+}}-.LJTI0_0

; LARGE-LABEL: test_jump_table:
; LARGE: bl .L0$pb
; LARGE: bcl 20, 31, .L0$pb
; LARGE-NEXT: .L0$pb:
; LARGE: mflr [[REGBASE:[0-9]+]]

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29 changes: 29 additions & 0 deletions llvm/test/CodeGen/PowerPC/ppc32-pic-bcl.ll
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@@ -0,0 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=powerpc -relocation-model=pic | \
; RUN: FileCheck -check-prefixes=SMALL %s

@val = global i8 0, align 1

define zeroext i8 @testbcl() nounwind {
; SMALL-LABEL: testbcl:
; SMALL: # %bb.0: # %entry
; SMALL-NEXT: mflr 0
; SMALL-NEXT: stwu 1, -16(1)
; SMALL-NEXT: stw 30, 8(1)
; SMALL-NEXT: stw 0, 20(1)
; SMALL-NEXT: bcl 20, 31, .L0$pb
; SMALL-NEXT: .L0$pb:
; SMALL-NEXT: mflr 30
; SMALL-NEXT: lwz 3, .L0$poff-.L0$pb(30)
; SMALL-NEXT: add 30, 3, 30
; SMALL-NEXT: lwz 3, .LC0-.LTOC(30)
; SMALL-NEXT: lbz 3, 0(3)
; SMALL-NEXT: lwz 0, 20(1)
; SMALL-NEXT: lwz 30, 8(1)
; SMALL-NEXT: addi 1, 1, 16
; SMALL-NEXT: mtlr 0
; SMALL-NEXT: blr
entry:
%0 = load i8, ptr @val, align 1
ret i8 %0
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll
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Expand Up @@ -55,7 +55,7 @@ entry:
; LARGE-BSS-NEXT: foo:
; LARGE-BSS: stwu 1, -32(1)
; LARGE-BSS: stw 30, 24(1)
; LARGE-BSS: bl [[PB]]
; LARGE-BSS: bcl 20, 31, [[PB]]
; LARGE-BSS-NEXT: [[PB]]:
; LARGE-BSS: mflr 30
; LARGE-BSS: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30)
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/ppc32-pic.ll
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Expand Up @@ -19,7 +19,7 @@ entry:
; SMALL: stwu 1, -32(1)
; SMALL: stw 30, 24(1)
; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_@local-4
; SMALL-SECURE: bl .L0$pb
; SMALL-SECURE: bcl 20, 31, .L0$pb
; SMALL: mflr 30
; SMALL-SECURE: addis 30, 30, _GLOBAL_OFFSET_TABLE_-.L0$pb@ha
; SMALL-SECURE: addi 30, 30, _GLOBAL_OFFSET_TABLE_-.L0$pb@l
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