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Merged
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Apr 4, 2025
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[PowerPC] Fix instruction name for dmr insert #134301

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4 changes: 2 additions & 2 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Expand Up @@ -11814,11 +11814,11 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
}

SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTFDMR512, dl, MVT::v512i1, Loads[0],
SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1, Loads[0],
Loads[1]),
0);
SDValue LoSub = DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32);
SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTFDMR512_HI, dl, MVT::v512i1,
SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
Loads[2], Loads[3]),
0);
SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
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Expand Up @@ -174,25 +174,25 @@ let Predicates = [IsISAFuture] in {
let P = 1;
}

def DMXXINSTFDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
def DMXXINSTDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
"dmxxinstfdmr512 $AT, $XAp, $XBp, 0", []> {
"dmxxinstdmr512 $AT, $XAp, $XBp, 0", []> {
let P = 0;
}

def DMXXINSTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
def DMXXINSTDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
"dmxxinstfdmr512 $AT, $XAp, $XBp, 1", []> {
"dmxxinstdmr512 $AT, $XAp, $XBp, 1", []> {
let P = 1;
}

def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp),
(ins dmrrowp:$AT, u2imm:$P),
"dmxxextfdmr256 $XBp, $AT, $P", []>;

def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
def DMXXINSTDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
(ins vsrprc:$XBp, u2imm:$P),
"dmxxinstfdmr256 $AT, $XBp, $P", []>;
"dmxxinstdmr256 $AT, $XBp, $P", []>;

def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
"dmmr $AT, $AB",
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/PowerPC/PPCInstrMMA.td
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Expand Up @@ -1089,9 +1089,9 @@ let Predicates = [MMA, IsNotISAFuture] in {

let Predicates = [MMA, IsISAFuture] in {
def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
(DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
(DMXXINSTDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
v16i8:$vs3, v16i8:$vs2)),
(DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
(DMXXINSTDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
def : Pat<(v512i1 immAllZerosV), (XXSETACCZW)>;
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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Expand Up @@ -1448,7 +1448,7 @@ void PPCRegisterInfo::lowerWACCRestore(MachineBasicBlock::iterator II,
FrameIndex, IsLittleEndian ? 0 : 32);

// Kill VSRpReg0, VSRpReg1 (killedRegState::Killed)
BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTFDMR512), DestReg)
BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTDMR512), DestReg)
.addReg(VSRpReg0, RegState::Kill)
.addReg(VSRpReg1, RegState::Kill);

Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
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Expand Up @@ -51,10 +51,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxv v2, 16(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
Expand All @@ -71,10 +71,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
Expand Down Expand Up @@ -102,10 +102,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxv v2, 16(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
Expand All @@ -122,10 +122,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
Expand Down Expand Up @@ -153,10 +153,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxv v2, 16(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
Expand All @@ -173,10 +173,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
Expand Down Expand Up @@ -242,10 +242,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxv v2, 16(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
Expand All @@ -262,10 +262,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/PowerPC/dmr-enable.ll
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Expand Up @@ -39,10 +39,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmmr dmr0, dmr0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r4)
Expand All @@ -56,10 +56,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmmr dmr0, dmr0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
Expand All @@ -80,16 +80,16 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxvp vsp34, 0(r4)
; CHECK-NEXT: lxvp vsp36, 32(r4)
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r4)
; CHECK-NEXT: lxvp vsp36, 96(r4)
; CHECK-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0
; CHECK-NEXT: dmxor dmr0, dmr1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
Expand All @@ -103,16 +103,16 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxvp vsp34, 96(r4)
; CHECK-BE-NEXT: lxvp vsp36, 64(r4)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r4)
; CHECK-BE-NEXT: lxvp vsp36, 0(r4)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxor dmr0, dmr1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
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Expand Up @@ -35,15 +35,15 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-NEXT: vmr v28, v2
; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; CHECK-NEXT: ld r30, 272(r1)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp60, vsp62, 0
; CHECK-NEXT: xvf16ger2pp wacc0, v2, v4
; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
; CHECK-NEXT: stxvp vsp36, 64(r1)
; CHECK-NEXT: stxvp vsp34, 32(r1)
; CHECK-NEXT: bl foo@notoc
; CHECK-NEXT: lxvp vsp34, 64(r1)
; CHECK-NEXT: lxvp vsp36, 32(r1)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
; CHECK-NEXT: xvf16ger2pp wacc0, v28, v30
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r30)
Expand Down Expand Up @@ -82,7 +82,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: vmr v28, v2
; CHECK-BE-NEXT: std r30, 240(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: ld r30, 368(r1)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp60, vsp62, 0
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v2, v4
; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 112(r1)
Expand All @@ -91,7 +91,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: lxvp vsp34, 112(r1)
; CHECK-BE-NEXT: lxvp vsp36, 144(r1)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v28, v30
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r30)
Expand Down
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