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[AMDGPU] Remove GCNRewritePartialRegUsesImpl::getOperandRegClass #135153

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[AMDGPU] Remove GCNRewritePartialRegUsesImpl::getOperandRegClass #135153

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18 changes: 0 additions & 18 deletions llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -105,9 +105,6 @@ class GCNRewritePartialRegUsesImpl {

/// Helper methods.

/// Return reg class expected by a MO's parent instruction for a given MO.
const TargetRegisterClass *getOperandRegClass(MachineOperand &MO) const;

/// Find right-shifted by RShift amount version of the SubReg if it exists,
/// return 0 otherwise.
unsigned shiftSubReg(unsigned SubReg, unsigned RShift) const;
Expand Down Expand Up @@ -404,13 +401,6 @@ void GCNRewritePartialRegUsesImpl::updateLiveIntervals(
LIS->removeInterval(OldReg);
}

const TargetRegisterClass *
GCNRewritePartialRegUsesImpl::getOperandRegClass(MachineOperand &MO) const {
MachineInstr *MI = MO.getParent();
return TII->getRegClass(TII->get(MI->getOpcode()), MI->getOperandNo(&MO), TRI,
*MI->getParent()->getParent());
}

bool GCNRewritePartialRegUsesImpl::rewriteReg(Register Reg) const {
auto Range = MRI->reg_nodbg_operands(Reg);
if (Range.empty() || any_of(Range, [](MachineOperand &MO) {
Expand All @@ -436,14 +426,6 @@ bool GCNRewritePartialRegUsesImpl::rewriteReg(Register Reg) const {
if (Inserted)
SubRegRC = TRI->getSubRegisterClass(RC, SubReg);

if (SubRegRC) {
if (const TargetRegisterClass *OpDescRC = getOperandRegClass(MO)) {
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I can't find any test case where this is needed. If getSubRegisterClass returns an exact match (i.e. not a superclass of what you ask for) then I guess it doesn't need to be constrained any more than the original RC was.

LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << " & "
<< TRI->getRegClassName(OpDescRC) << " = ");
SubRegRC = TRI->getCommonSubClass(SubRegRC, OpDescRC);
}
}

if (!SubRegRC) {
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I suspect this can be an assert now.

LLVM_DEBUG(dbgs() << "couldn't find target regclass\n");
return false;
Expand Down