[AMDGPU] Rename TH_STORE_RT_WB to TH_STORE_WB #135171
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So it matches the documentation
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-mc Author: Mirko Brkušanin (mbrkusanin) ChangesSo it matches the documentation Full diff: https://github.com/llvm/llvm-project/pull/135171.diff 9 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index c48bcda167f57..7ef6285ce7b1f 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -6776,7 +6776,7 @@ ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
if (Value == "TH_DEFAULT")
TH = AMDGPU::CPol::TH_RT;
- else if (Value == "TH_STORE_LU" || Value == "TH_LOAD_RT_WB" ||
+ else if (Value == "TH_STORE_LU" || Value == "TH_LOAD_WB" ||
Value == "TH_LOAD_NT_WB") {
return Error(StringLoc, "invalid th value");
} else if (Value.consume_front("TH_ATOMIC_")) {
@@ -6811,7 +6811,7 @@ ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
.Case("NT", AMDGPU::CPol::TH_NT)
.Case("HT", AMDGPU::CPol::TH_HT)
.Case("LU", AMDGPU::CPol::TH_LU)
- .Case("RT_WB", AMDGPU::CPol::TH_RT_WB)
+ .Case("WB", AMDGPU::CPol::TH_WB)
.Case("NT_RT", AMDGPU::CPol::TH_NT_RT)
.Case("RT_NT", AMDGPU::CPol::TH_RT_NT)
.Case("NT_HT", AMDGPU::CPol::TH_NT_HT)
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 381841f142855..caff8be3d7348 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -206,9 +206,9 @@ void AMDGPUInstPrinter::printTH(const MCInst *MI, int64_t TH, int64_t Scope,
case AMDGPU::CPol::TH_HT:
O << "HT";
break;
- case AMDGPU::CPol::TH_BYPASS: // or LU or RT_WB
+ case AMDGPU::CPol::TH_BYPASS: // or LU or WB
O << (Scope == AMDGPU::CPol::SCOPE_SYS ? "BYPASS"
- : (IsStore ? "RT_WB" : "LU"));
+ : (IsStore ? "WB" : "LU"));
break;
case AMDGPU::CPol::TH_NT_RT:
O << "NT_RT";
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 8e811b43a4532..9f0dcdb9dc9a3 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -396,7 +396,7 @@ enum CPol {
TH_NT = 1, // non-temporal
TH_HT = 2, // high-temporal
TH_LU = 3, // last use
- TH_RT_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
+ TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
index 21482ba1adc1e..8e37d2fd67466 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
@@ -1097,7 +1097,7 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
;
; GFX12-LABEL: store_1d_glc_slc:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB a16
+; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB a16
; GFX12-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
index dca5e671ab58f..69720ac5d8058 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
@@ -1354,7 +1354,7 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
;
; GFX12-LABEL: store_1d_glc_slc:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB a16 ; encoding: [0x40,0x80,0xc1,0xd3,0x00,0x00,0x30,0x00,0x04,0x00,0x00,0x00]
+; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB a16 ; encoding: [0x40,0x80,0xc1,0xd3,0x00,0x00,0x30,0x00,0x04,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
index 2fced3240fe35..beed45339c8a3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
@@ -3837,7 +3837,7 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
;
; GFX12-LABEL: store_1d_glc_slc:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB
+; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB
; GFX12-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3)
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
index c99123bbe1ee0..1a3baed75efbb 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
@@ -393,7 +393,7 @@ image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_HT
// GFX12: encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
-image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_WB
// GFX12: encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_RT
diff --git a/llvm/test/MC/AMDGPU/gfx12_err.s b/llvm/test/MC/AMDGPU/gfx12_err.s
index 5269288f9d1e8..9ddb91e25afe6 100644
--- a/llvm/test/MC/AMDGPU/gfx12_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_err.s
@@ -82,13 +82,13 @@ image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_LU
// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid th value
-image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_RT_WB
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_WB
// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid th value
image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_WB
// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid th value
-image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB scope:SCOPE_SYS
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_WB scope:SCOPE_SYS
// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: scope and th combination is not valid
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_BYPASS scope:SCOPE_DEV
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
index 387bdf5a6018f..85fbd82543c5f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
@@ -394,7 +394,7 @@
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_HT ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
0x00,0x80,0x41,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00
-# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
+# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_WB ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
0x00,0x80,0x41,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_RT ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00]
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Pierre-vh
approved these changes
Apr 10, 2025
var-const
pushed a commit
to ldionne/llvm-project
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Apr 17, 2025
So it matches the documentation Fixes: SWDEV-526726
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So it matches the documentation
Fixes: SWDEV-526726