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Apr 10, 2025
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Support z17 processor name and scheduler description #135254

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2 changes: 1 addition & 1 deletion clang/lib/Basic/Targets/SystemZ.cpp
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Expand Up @@ -114,7 +114,7 @@ static constexpr ISANameRevision ISARevisions[] = {
{{"arch12"}, 12}, {{"z14"}, 12},
{{"arch13"}, 13}, {{"z15"}, 13},
{{"arch14"}, 14}, {{"z16"}, 14},
{{"arch15"}, 15},
{{"arch15"}, 15}, {{"z17"}, 15},
};

int SystemZTargetInfo::getISARevision(StringRef Name) const {
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4 changes: 2 additions & 2 deletions clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c
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@@ -1,6 +1,6 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s

unsigned long test_bdepg(unsigned long a, unsigned long b) {
// CHECK-LABEL: test_bdepg
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2 changes: 1 addition & 1 deletion clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c
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@@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-unknown-unknown \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-unknown-unknown \
// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s

typedef __attribute__((vector_size(16))) signed char vec_schar;
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2 changes: 1 addition & 1 deletion clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c
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@@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -flax-vector-conversions=none \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s

typedef __attribute__((vector_size(16))) signed char vec_schar;
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2 changes: 1 addition & 1 deletion clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c
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@@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s

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4 changes: 2 additions & 2 deletions clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
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@@ -1,8 +1,8 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -O2 -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -O2 -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM

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2 changes: 2 additions & 0 deletions clang/test/CodeGen/SystemZ/systemz-abi-vector.c
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Expand Up @@ -18,6 +18,8 @@
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu z17 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s

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2 changes: 2 additions & 0 deletions clang/test/CodeGen/SystemZ/systemz-abi.c
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Expand Up @@ -24,6 +24,8 @@
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s -mfloat-abi soft | FileCheck %s \
// RUN: --check-prefixes=CHECK,SOFT-FLOAT
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu z17 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
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2 changes: 2 additions & 0 deletions clang/test/Driver/systemz-march.c
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Expand Up @@ -15,6 +15,7 @@
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch13 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH13 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=z16 %s 2>&1 | FileCheck --check-prefix=CHECK-Z16 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch14 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH14 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=z17 %s 2>&1 | FileCheck --check-prefix=CHECK-Z17 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch15 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH15 %s

// CHECK-Z9: error: unknown target CPU 'z9'
Expand All @@ -32,6 +33,7 @@
// CHECK-ARCH13: "-target-cpu" "arch13"
// CHECK-Z16: "-target-cpu" "z16"
// CHECK-ARCH14: "-target-cpu" "arch14"
// CHECK-Z17: "-target-cpu" "z17"
// CHECK-ARCH15: "-target-cpu" "arch15"

int x;
1 change: 1 addition & 0 deletions clang/test/Misc/target-invalid-cpu-note/systemz.c
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Expand Up @@ -20,4 +20,5 @@
// CHECK-SAME: {{^}}, arch14
// CHECK-SAME: {{^}}, z16
// CHECK-SAME: {{^}}, arch15
// CHECK-SAME: {{^}}, z17
// CHECK-SAME: {{$}}
3 changes: 3 additions & 0 deletions clang/test/Preprocessor/predefined-arch-macros.c
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Expand Up @@ -4394,6 +4394,9 @@
// RUN: %clang -march=arch15 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH15
// RUN: %clang -march=z17 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH15
// CHECK_SYSTEMZ_ARCH15: #define __ARCH__ 15
// CHECK_SYSTEMZ_ARCH15: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH15: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
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10 changes: 5 additions & 5 deletions llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
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Expand Up @@ -258,7 +258,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FSHL, MVT::i128, Custom);
setOperationAction(ISD::FSHR, MVT::i128, Custom);

// No special instructions for these before arch15.
// No special instructions for these before z17.
if (!Subtarget.hasVectorEnhancements3()) {
setOperationAction(ISD::MUL, MVT::i128, Expand);
setOperationAction(ISD::MULHS, MVT::i128, Expand);
Expand All @@ -285,7 +285,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
// Use VPOPCT and add up partial results.
setOperationAction(ISD::CTPOP, MVT::i128, Custom);

// Additional instructions available with arch15.
// Additional instructions available with z17.
if (Subtarget.hasVectorEnhancements3()) {
setOperationAction(ISD::ABS, MVT::i128, Legal);
}
Expand Down Expand Up @@ -357,7 +357,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
setOperationAction(ISD::CTLZ, MVT::i64, Legal);

// On arch15 we have native support for a 64-bit CTTZ.
// On z17 we have native support for a 64-bit CTTZ.
if (Subtarget.hasMiscellaneousExtensions4()) {
setOperationAction(ISD::CTTZ, MVT::i32, Promote);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Promote);
Expand Down Expand Up @@ -4526,7 +4526,7 @@ SDValue SystemZTargetLowering::lowerMULH(SDValue Op,
SDLoc DL(Op);
SDValue Even, Odd;

// This custom expander is only used on arch15 and later for 64-bit types.
// This custom expander is only used on z17 and later for 64-bit types.
assert(!is32Bit(VT));
assert(Subtarget.hasMiscellaneousExtensions2());

Expand Down Expand Up @@ -8733,7 +8733,7 @@ static unsigned detectEvenOddMultiplyOperand(const SelectionDAG &DAG,
}
}

// For arch15, we can also support the v2i64->i128 case, which looks like
// For z17, we can also support the v2i64->i128 case, which looks like
// (sign/zero_extend (extract_vector_elt X 0/1))
if (VT == MVT::i128 && Subtarget.hasVectorEnhancements3() &&
(Op.getOpcode() == ISD::SIGN_EXTEND ||
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8 changes: 4 additions & 4 deletions llvm/lib/Target/SystemZ/SystemZInstrVector.td
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Expand Up @@ -1995,7 +1995,7 @@ let Predicates = [FeatureVector] in {
(VLEG (VGBM 0), bdxaddr12only:$addr, 1)>;
}

// Zero-extensions from VR element to i128 on arch15.
// Zero-extensions from VR element to i128 on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (zext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),
(VUPLHG VR128:$src)>;
Expand All @@ -2011,7 +2011,7 @@ let Predicates = [FeatureVectorEnhancements3] in {
(VUPLLG (VUPLLF VR128:$src))>;
}

// In-register i128 sign-extensions on arch15.
// In-register i128 sign-extensions on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (sext_inreg VR128:$x, i8)), (VUPLG (VSEGB VR128:$x))>;
def : Pat<(i128 (sext_inreg VR128:$x, i16)), (VUPLG (VSEGH VR128:$x))>;
Expand All @@ -2031,7 +2031,7 @@ let Predicates = [FeatureVector] in {
(VSRAB (VREPG VR128:$x, 1), (VREPIB 64))>;
}

// Sign-extensions from GPR to i128 on arch15.
// Sign-extensions from GPR to i128 on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)),
(VUPLG (VLVGP (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32)),
Expand Down Expand Up @@ -2075,7 +2075,7 @@ let Predicates = [FeatureVector] in {
(VSRAB (VLREPG bdxaddr12only:$addr), (VREPIB 64))>;
}

// Sign-extensions from VR element to i128 on arch15.
// Sign-extensions from VR element to i128 on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (sext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),
(VUPHG VR128:$src)>;
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3 changes: 2 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZProcessors.td
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Expand Up @@ -41,4 +41,5 @@ def : ProcessorModel<"z15", Z15Model, Arch13SupportedFeatures.List>;
def : ProcessorModel<"arch14", Z16Model, Arch14SupportedFeatures.List>;
def : ProcessorModel<"z16", Z16Model, Arch14SupportedFeatures.List>;

def : ProcessorModel<"arch15", Z16Model, Arch15SupportedFeatures.List>;
def : ProcessorModel<"arch15", Z17Model, Arch15SupportedFeatures.List>;
def : ProcessorModel<"z17", Z17Model, Arch15SupportedFeatures.List>;
1 change: 1 addition & 0 deletions llvm/lib/Target/SystemZ/SystemZSchedule.td
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Expand Up @@ -60,6 +60,7 @@ def VBU : SchedWrite; // Virtual branching unit

def MCD : SchedWrite; // Millicode

include "SystemZScheduleZ17.td"
include "SystemZScheduleZ16.td"
include "SystemZScheduleZ15.td"
include "SystemZScheduleZ14.td"
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16 changes: 8 additions & 8 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
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Expand Up @@ -1555,12 +1555,12 @@ def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "V(T|C)P$")>;

def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VSCH(S|D|X)?P$")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VSCSHP$")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VCSPH")>;
def : InstRW<[WLat2, WLat2, VecXsPm, NormalGr], (instregex "VCLZDP")>;
def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRPR")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VPKZR")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZH")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZL")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VCSPH$")>;
def : InstRW<[WLat2, WLat2, VecXsPm, NormalGr], (instregex "VCLZDP$")>;
def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRPR$")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VPKZR$")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZH$")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZL$")>;

// -------------------------------- System ---------------------------------- //

Expand Down Expand Up @@ -1597,8 +1597,8 @@ def : InstRW<[WLat30, MCD], (instregex "S(T)?PX$")>;
// System: Breaking-Event-Address-Register Instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LBEAR")>;
def : InstRW<[WLat1, LSU2, FXb, GroupAlone], (instregex "STBEAR")>;
def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LBEAR$")>;
def : InstRW<[WLat1, LSU2, FXb, GroupAlone], (instregex "STBEAR$")>;

//===----------------------------------------------------------------------===//
// System: Storage-Key and Real Memory Instructions
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