[AMDGPU][InstCombine][InstSimplify] Pre-commit tests for PR130742

llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll

@@ -135,7 +135,7 @@ alive:
 
 ; This is reduced test case catching regression in the first version of the
 ; fix for invariant loads (https://reviews.llvm.org/D64405).
-define void @test4() {
+define void @test4() null_pointer_is_valid {
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load float, ptr inttoptr (i64 8 to ptr), align 4

llvm/test/Analysis/ValueTracking/gep-negative-issue.ll

@@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gnu"
 %ArrayImpl = type { i64, ptr addrspace(100), [1 x i64], [1 x i64], [1 x i64], i64, i64, ptr addrspace(100), ptr addrspace(100), i8, i64 }
 %_array = type { i64, ptr addrspace(100), i8 }
 
-define void @test(i64 %n_chpl) {
+define void @test(i64 %n_chpl) null_pointer_is_valid {
 entry:
   ; First section is some code
   %0 = getelementptr inbounds %_array, ptr null, i32 0, i32 1

llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

@@ -402,39 +402,68 @@ bb:
   ret <2 x half> %result
 }
 
-define <2 x half> @chain_hi_to_lo_flat() {
-; GCN-LABEL: chain_hi_to_lo_flat:
-; GCN:       ; %bb.0: ; %bb
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v0, 2
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    flat_load_ushort v0, v[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
-; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN-NEXT:    flat_load_short_d16_hi v0, v[1:2]
-; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+define <2 x half> @chain_hi_to_lo_flat(ptr inreg %ptr) {
+; GFX900-LABEL: chain_hi_to_lo_flat:
+; GFX900:       ; %bb.0: ; %bb
+; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT:    v_mov_b32_e32 v0, s16
+; GFX900-NEXT:    v_mov_b32_e32 v1, s17
+; GFX900-NEXT:    flat_load_ushort v0, v[0:1] offset:2
+; GFX900-NEXT:    v_mov_b32_e32 v1, 0
+; GFX900-NEXT:    v_mov_b32_e32 v2, 0
+; GFX900-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT:    flat_load_short_d16_hi v0, v[1:2]
+; GFX900-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: chain_hi_to_lo_flat:
-; GFX10:       ; %bb.0: ; %bb
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, 2
-; GFX10-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10-NEXT:    flat_load_ushort v0, v[0:1]
-; GFX10-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10-NEXT:    v_mov_b32_e32 v2, 0
-; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    flat_load_short_d16_hi v0, v[1:2]
-; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; FLATSCR-LABEL: chain_hi_to_lo_flat:
+; FLATSCR:       ; %bb.0: ; %bb
+; FLATSCR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FLATSCR-NEXT:    v_mov_b32_e32 v0, s0
+; FLATSCR-NEXT:    v_mov_b32_e32 v1, s1
+; FLATSCR-NEXT:    flat_load_ushort v0, v[0:1] offset:2
+; FLATSCR-NEXT:    v_mov_b32_e32 v1, 0
+; FLATSCR-NEXT:    v_mov_b32_e32 v2, 0
+; FLATSCR-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; FLATSCR-NEXT:    flat_load_short_d16_hi v0, v[1:2]
+; FLATSCR-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; FLATSCR-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10_DEFAULT-LABEL: chain_hi_to_lo_flat:
+; GFX10_DEFAULT:       ; %bb.0: ; %bb
+; GFX10_DEFAULT-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10_DEFAULT-NEXT:    s_add_u32 s4, s16, 2
+; GFX10_DEFAULT-NEXT:    s_addc_u32 s5, s17, 0
+; GFX10_DEFAULT-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10_DEFAULT-NEXT:    v_mov_b32_e32 v1, s5
+; GFX10_DEFAULT-NEXT:    flat_load_ushort v0, v[0:1]
+; GFX10_DEFAULT-NEXT:    v_mov_b32_e32 v1, 0
+; GFX10_DEFAULT-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10_DEFAULT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX10_DEFAULT-NEXT:    flat_load_short_d16_hi v0, v[1:2]
+; GFX10_DEFAULT-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX10_DEFAULT-NEXT:    s_setpc_b64 s[30:31]
+;
+; FLATSCR_GFX10-LABEL: chain_hi_to_lo_flat:
+; FLATSCR_GFX10:       ; %bb.0: ; %bb
+; FLATSCR_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FLATSCR_GFX10-NEXT:    s_add_u32 s0, s0, 2
+; FLATSCR_GFX10-NEXT:    s_addc_u32 s1, s1, 0
+; FLATSCR_GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; FLATSCR_GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; FLATSCR_GFX10-NEXT:    flat_load_ushort v0, v[0:1]
+; FLATSCR_GFX10-NEXT:    v_mov_b32_e32 v1, 0
+; FLATSCR_GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; FLATSCR_GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; FLATSCR_GFX10-NEXT:    flat_load_short_d16_hi v0, v[1:2]
+; FLATSCR_GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; FLATSCR_GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-TRUE16-LABEL: chain_hi_to_lo_flat:
 ; GFX11-TRUE16:       ; %bb.0: ; %bb
 ; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 2
-; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT:    flat_load_d16_b16 v0, v[0:1]
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT:    flat_load_d16_b16 v0, v[0:1] offset:2
 ; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -445,17 +474,16 @@ define <2 x half> @chain_hi_to_lo_flat() {
 ; GFX11-FAKE16-LABEL: chain_hi_to_lo_flat:
 ; GFX11-FAKE16:       ; %bb.0: ; %bb
 ; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 2
-; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT:    flat_load_u16 v0, v[0:1]
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-FAKE16-NEXT:    flat_load_u16 v0, v[0:1] offset:2
 ; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-FAKE16-NEXT:    flat_load_d16_hi_b16 v0, v[1:2]
 ; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 bb:
-  %gep_lo = getelementptr inbounds half, ptr null, i64 1
+  %gep_lo = getelementptr inbounds half, ptr %ptr, i64 1
   %load_lo = load half, ptr %gep_lo
   %load_hi = load half, ptr null
 

llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll

@@ -3,26 +3,28 @@
 
 %"struct.__llvm_libc::rpc::Buffer" = type { [8 x i64] }
 
-define void @issue63986(i64 %0, i64 %idxprom) {
+define void @issue63986(i64 %0, i64 %idxprom, ptr inreg %ptr) {
 ; CHECK-LABEL: issue63986:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_lshlrev_b64 v[4:5], 6, v[2:3]
+; CHECK-NEXT:    v_mov_b32_e32 v6, s17
+; CHECK-NEXT:    v_add_co_u32_e32 v8, vcc, s16, v4
+; CHECK-NEXT:    v_addc_co_u32_e32 v9, vcc, v6, v5, vcc
 ; CHECK-NEXT:    s_mov_b64 s[4:5], 0
 ; CHECK-NEXT:  .LBB0_1: ; %loop-memcpy-expansion
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    v_mov_b32_e32 v7, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v6, s4
-; CHECK-NEXT:    flat_load_dwordx4 v[6:9], v[6:7]
-; CHECK-NEXT:    v_add_co_u32_e32 v10, vcc, s4, v4
+; CHECK-NEXT:    flat_load_dwordx4 v[10:13], v[6:7]
+; CHECK-NEXT:    v_add_co_u32_e32 v6, vcc, s4, v8
 ; CHECK-NEXT:    s_add_u32 s4, s4, 16
-; CHECK-NEXT:    v_mov_b32_e32 v11, s5
 ; CHECK-NEXT:    s_addc_u32 s5, s5, 0
 ; CHECK-NEXT:    v_cmp_ge_u64_e64 s[6:7], s[4:5], 32
-; CHECK-NEXT:    v_addc_co_u32_e32 v11, vcc, v5, v11, vcc
+; CHECK-NEXT:    v_addc_co_u32_e32 v7, vcc, v9, v7, vcc
 ; CHECK-NEXT:    s_and_b64 vcc, exec, s[6:7]
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    flat_store_dwordx4 v[10:11], v[6:9]
+; CHECK-NEXT:    flat_store_dwordx4 v[6:7], v[10:13]
 ; CHECK-NEXT:    s_cbranch_vccz .LBB0_1
 ; CHECK-NEXT:  ; %bb.2: ; %loop-memcpy-residual-header
 ; CHECK-NEXT:    s_branch .LBB0_4
@@ -31,110 +33,116 @@ define void @issue63986(i64 %0, i64 %idxprom) {
 ; CHECK-NEXT:    s_branch .LBB0_5
 ; CHECK-NEXT:  .LBB0_4: ; %loop-memcpy-residual-header.post-loop-memcpy-expansion_crit_edge
 ; CHECK-NEXT:    v_lshlrev_b64 v[6:7], 6, v[2:3]
-; CHECK-NEXT:    s_cbranch_execnz .LBB0_7
+; CHECK-NEXT:    s_cbranch_execnz .LBB0_8
 ; CHECK-NEXT:  .LBB0_5: ; %loop-memcpy-residual.preheader
-; CHECK-NEXT:    v_or_b32_e32 v2, 32, v4
-; CHECK-NEXT:    v_mov_b32_e32 v3, v5
+; CHECK-NEXT:    s_add_u32 s4, s16, 32
+; CHECK-NEXT:    s_addc_u32 s5, s17, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, s5
+; CHECK-NEXT:    v_add_co_u32_e32 v2, vcc, s4, v4
+; CHECK-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
 ; CHECK-NEXT:    s_mov_b64 s[4:5], 0
 ; CHECK-NEXT:  ; %bb.6: ; %loop-memcpy-residual
 ; CHECK-NEXT:    s_add_u32 s6, 32, s4
 ; CHECK-NEXT:    s_addc_u32 s7, 0, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v6, s6
 ; CHECK-NEXT:    v_mov_b32_e32 v7, s7
 ; CHECK-NEXT:    flat_load_ubyte v10, v[6:7]
-; CHECK-NEXT:    v_mov_b32_e32 v9, s5
-; CHECK-NEXT:    v_add_co_u32_e32 v8, vcc, s4, v2
-; CHECK-NEXT:    v_mov_b32_e32 v7, v5
-; CHECK-NEXT:    v_addc_co_u32_e32 v9, vcc, v3, v9, vcc
+; CHECK-NEXT:    v_mov_b32_e32 v7, s5
+; CHECK-NEXT:    v_add_co_u32_e32 v6, vcc, s4, v2
+; CHECK-NEXT:    v_addc_co_u32_e32 v7, vcc, v3, v7, vcc
 ; CHECK-NEXT:    s_add_u32 s4, s4, 1
-; CHECK-NEXT:    v_mov_b32_e32 v6, v4
 ; CHECK-NEXT:    s_addc_u32 s5, s5, 0
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    flat_store_byte v[8:9], v10
-; CHECK-NEXT:  .LBB0_7: ; %post-loop-memcpy-expansion
+; CHECK-NEXT:    flat_store_byte v[6:7], v10
+; CHECK-NEXT:  ; %bb.7:
+; CHECK-NEXT:    v_mov_b32_e32 v7, v5
+; CHECK-NEXT:    v_mov_b32_e32 v6, v4
+; CHECK-NEXT:  .LBB0_8: ; %post-loop-memcpy-expansion
 ; CHECK-NEXT:    v_and_b32_e32 v2, 15, v0
-; CHECK-NEXT:    v_mov_b32_e32 v3, 0
 ; CHECK-NEXT:    v_and_b32_e32 v0, -16, v0
+; CHECK-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v1, vcc
 ; CHECK-NEXT:    v_cmp_ne_u64_e64 s[4:5], 0, v[0:1]
 ; CHECK-NEXT:    v_cmp_ne_u64_e64 s[6:7], 0, v[2:3]
-; CHECK-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v0
-; CHECK-NEXT:    v_addc_co_u32_e32 v7, vcc, v7, v1, vcc
-; CHECK-NEXT:    s_branch .LBB0_10
-; CHECK-NEXT:  .LBB0_8: ; %Flow14
-; CHECK-NEXT:    ; in Loop: Header=BB0_10 Depth=1
+; CHECK-NEXT:    v_mov_b32_e32 v6, s17
+; CHECK-NEXT:    v_add_co_u32_e32 v4, vcc, s16, v4
+; CHECK-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
+; CHECK-NEXT:    s_branch .LBB0_11
+; CHECK-NEXT:  .LBB0_9: ; %Flow14
+; CHECK-NEXT:    ; in Loop: Header=BB0_11 Depth=1
 ; CHECK-NEXT:    s_or_b64 exec, exec, s[10:11]
 ; CHECK-NEXT:    s_mov_b64 s[8:9], 0
-; CHECK-NEXT:  .LBB0_9: ; %Flow16
-; CHECK-NEXT:    ; in Loop: Header=BB0_10 Depth=1
+; CHECK-NEXT:  .LBB0_10: ; %Flow16
+; CHECK-NEXT:    ; in Loop: Header=BB0_11 Depth=1
 ; CHECK-NEXT:    s_andn2_b64 vcc, exec, s[8:9]
-; CHECK-NEXT:    s_cbranch_vccz .LBB0_18
-; CHECK-NEXT:  .LBB0_10: ; %while.cond
+; CHECK-NEXT:    s_cbranch_vccz .LBB0_19
+; CHECK-NEXT:  .LBB0_11: ; %while.cond
 ; CHECK-NEXT:    ; =>This Loop Header: Depth=1
-; CHECK-NEXT:    ; Child Loop BB0_12 Depth 2
-; CHECK-NEXT:    ; Child Loop BB0_16 Depth 2
+; CHECK-NEXT:    ; Child Loop BB0_13 Depth 2
+; CHECK-NEXT:    ; Child Loop BB0_17 Depth 2
 ; CHECK-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
-; CHECK-NEXT:    s_cbranch_execz .LBB0_13
-; CHECK-NEXT:  ; %bb.11: ; %loop-memcpy-expansion2.preheader
-; CHECK-NEXT:    ; in Loop: Header=BB0_10 Depth=1
+; CHECK-NEXT:    s_cbranch_execz .LBB0_14
+; CHECK-NEXT:  ; %bb.12: ; %loop-memcpy-expansion2.preheader
+; CHECK-NEXT:    ; in Loop: Header=BB0_11 Depth=1
 ; CHECK-NEXT:    s_mov_b64 s[10:11], 0
 ; CHECK-NEXT:    s_mov_b64 s[12:13], 0
-; CHECK-NEXT:  .LBB0_12: ; %loop-memcpy-expansion2
-; CHECK-NEXT:    ; Parent Loop BB0_10 Depth=1
+; CHECK-NEXT:  .LBB0_13: ; %loop-memcpy-expansion2
+; CHECK-NEXT:    ; Parent Loop BB0_11 Depth=1
 ; CHECK-NEXT:    ; => This Inner Loop Header: Depth=2
-; CHECK-NEXT:    v_mov_b32_e32 v8, s12
-; CHECK-NEXT:    v_mov_b32_e32 v9, s13
-; CHECK-NEXT:    flat_load_dwordx4 v[8:11], v[8:9]
-; CHECK-NEXT:    v_mov_b32_e32 v13, s13
-; CHECK-NEXT:    v_add_co_u32_e32 v12, vcc, s12, v4
+; CHECK-NEXT:    v_mov_b32_e32 v6, s12
+; CHECK-NEXT:    v_mov_b32_e32 v7, s13
+; CHECK-NEXT:    flat_load_dwordx4 v[10:13], v[6:7]
+; CHECK-NEXT:    v_add_co_u32_e32 v6, vcc, s12, v8
 ; CHECK-NEXT:    s_add_u32 s12, s12, 16
-; CHECK-NEXT:    v_addc_co_u32_e32 v13, vcc, v5, v13, vcc
+; CHECK-NEXT:    v_addc_co_u32_e32 v7, vcc, v9, v7, vcc
 ; CHECK-NEXT:    s_addc_u32 s13, s13, 0
 ; CHECK-NEXT:    v_cmp_ge_u64_e32 vcc, s[12:13], v[0:1]
 ; CHECK-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    flat_store_dwordx4 v[12:13], v[8:11]
+; CHECK-NEXT:    flat_store_dwordx4 v[6:7], v[10:13]
 ; CHECK-NEXT:    s_andn2_b64 exec, exec, s[10:11]
-; CHECK-NEXT:    s_cbranch_execnz .LBB0_12
-; CHECK-NEXT:  .LBB0_13: ; %Flow15
-; CHECK-NEXT:    ; in Loop: Header=BB0_10 Depth=1
+; CHECK-NEXT:    s_cbranch_execnz .LBB0_13
+; CHECK-NEXT:  .LBB0_14: ; %Flow15
+; CHECK-NEXT:    ; in Loop: Header=BB0_11 Depth=1
 ; CHECK-NEXT:    s_or_b64 exec, exec, s[8:9]
 ; CHECK-NEXT:    s_mov_b64 s[8:9], -1
-; CHECK-NEXT:    s_cbranch_execz .LBB0_9
-; CHECK-NEXT:  ; %bb.14: ; %loop-memcpy-residual-header5
-; CHECK-NEXT:    ; in Loop: Header=BB0_10 Depth=1
+; CHECK-NEXT:    s_cbranch_execz .LBB0_10
+; CHECK-NEXT:  ; %bb.15: ; %loop-memcpy-residual-header5
+; CHECK-NEXT:    ; in Loop: Header=BB0_11 Depth=1
 ; CHECK-NEXT:    s_and_saveexec_b64 s[8:9], s[6:7]
 ; CHECK-NEXT:    s_xor_b64 s[10:11], exec, s[8:9]
-; CHECK-NEXT:    s_cbranch_execz .LBB0_8
-; CHECK-NEXT:  ; %bb.15: ; %loop-memcpy-residual4.preheader
-; CHECK-NEXT:    ; in Loop: Header=BB0_10 Depth=1
+; CHECK-NEXT:    s_cbranch_execz .LBB0_9
+; CHECK-NEXT:  ; %bb.16: ; %loop-memcpy-residual4.preheader
+; CHECK-NEXT:    ; in Loop: Header=BB0_11 Depth=1
 ; CHECK-NEXT:    s_mov_b64 s[12:13], 0
 ; CHECK-NEXT:    s_mov_b64 s[14:15], 0
-; CHECK-NEXT:  .LBB0_16: ; %loop-memcpy-residual4
-; CHECK-NEXT:    ; Parent Loop BB0_10 Depth=1
+; CHECK-NEXT:  .LBB0_17: ; %loop-memcpy-residual4
+; CHECK-NEXT:    ; Parent Loop BB0_11 Depth=1
 ; CHECK-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    v_mov_b32_e32 v10, s15
-; CHECK-NEXT:    v_add_co_u32_e32 v8, vcc, s14, v0
-; CHECK-NEXT:    v_addc_co_u32_e32 v9, vcc, v1, v10, vcc
-; CHECK-NEXT:    flat_load_ubyte v11, v[8:9]
-; CHECK-NEXT:    v_add_co_u32_e32 v8, vcc, s14, v6
+; CHECK-NEXT:    v_add_co_u32_e32 v6, vcc, s14, v0
+; CHECK-NEXT:    v_addc_co_u32_e32 v7, vcc, v1, v10, vcc
+; CHECK-NEXT:    flat_load_ubyte v11, v[6:7]
+; CHECK-NEXT:    v_add_co_u32_e32 v6, vcc, s14, v4
 ; CHECK-NEXT:    s_add_u32 s14, s14, 1
 ; CHECK-NEXT:    s_addc_u32 s15, s15, 0
 ; CHECK-NEXT:    v_cmp_ge_u64_e64 s[8:9], s[14:15], v[2:3]
-; CHECK-NEXT:    v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
+; CHECK-NEXT:    v_addc_co_u32_e32 v7, vcc, v5, v10, vcc
 ; CHECK-NEXT:    s_or_b64 s[12:13], s[8:9], s[12:13]
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    flat_store_byte v[8:9], v11
+; CHECK-NEXT:    flat_store_byte v[6:7], v11
 ; CHECK-NEXT:    s_andn2_b64 exec, exec, s[12:13]
-; CHECK-NEXT:    s_cbranch_execnz .LBB0_16
-; CHECK-NEXT:  ; %bb.17: ; %Flow
-; CHECK-NEXT:    ; in Loop: Header=BB0_10 Depth=1
+; CHECK-NEXT:    s_cbranch_execnz .LBB0_17
+; CHECK-NEXT:  ; %bb.18: ; %Flow
+; CHECK-NEXT:    ; in Loop: Header=BB0_11 Depth=1
 ; CHECK-NEXT:    s_or_b64 exec, exec, s[12:13]
-; CHECK-NEXT:    s_branch .LBB0_8
-; CHECK-NEXT:  .LBB0_18: ; %DummyReturnBlock
+; CHECK-NEXT:    s_branch .LBB0_9
+; CHECK-NEXT:  .LBB0_19: ; %DummyReturnBlock
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
 entry:
-  %arrayidx = getelementptr [32 x %"struct.__llvm_libc::rpc::Buffer"], ptr null, i64 0, i64 %idxprom
+  %arrayidx = getelementptr [32 x %"struct.__llvm_libc::rpc::Buffer"], ptr %ptr, i64 0, i64 %idxprom
   %spec.select = tail call i64 @llvm.umin.i64(i64 sub (i64 ptrtoint (ptr addrspacecast (ptr addrspace(4) inttoptr (i64 32 to ptr addrspace(4)) to ptr) to i64), i64 ptrtoint (ptr addrspacecast (ptr addrspace(4) null to ptr) to i64)), i64 56)
   tail call void @llvm.memcpy.p0.p0.i64(ptr %arrayidx, ptr null, i64 %spec.select, i1 false)
   br label %while.cond

llvm/test/Transforms/GVN/constexpr-vector-constainsundef-crash-inseltpoison.ll

@@ -5,7 +5,7 @@
 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=24278
 
 ; Make sure we do not crash when dealing with a vector constant expression.
-define <4 x ptr> @test(ptr %ptr) {
+define <4 x ptr> @test(ptr %ptr) null_pointer_is_valid {
 ; CHECK-LABEL: @test(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[L3:%.*]] = load i64, ptr [[PTR:%.*]], align 4

llvm/test/Transforms/GVN/constexpr-vector-constainsundef-crash.ll

@@ -5,7 +5,7 @@
 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=24278
 
 ; Make sure we do not crash when dealing with a vector constant expression.
-define <4 x ptr> @test(ptr %ptr) {
+define <4 x ptr> @test(ptr %ptr) null_pointer_is_valid {
 ; CHECK-LABEL: @test(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[L3:%.*]] = load i64, ptr [[PTR:%.*]], align 4

llvm/test/Transforms/InstSimplify/ConstProp/cast-vector.ll

@@ -5,7 +5,7 @@
 ; "offsetof-like expression" case).
 ; This used to hit an assert due to not supporting vectors in
 ; llvm::ConstantFoldCastInstruction when handling ptrtoint.
-define <2 x i16> @test1() {
+define <2 x i16> @test1() null_pointer_is_valid {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    ret <2 x i16> <i16 ptrtoint (ptr getelementptr inbounds ([10 x i32], ptr null, i64 0, i64 5) to i16), i16 ptrtoint (ptr getelementptr inbounds ([10 x i32], ptr null, i64 0, i64 7) to i16)>
@@ -20,7 +20,7 @@ entry:
 ; "sizeof-like expression" case).
 ; This used to hit an assert due to not supporting vectors in
 ; llvm::ConstantFoldCastInstruction when handling ptrtoint.
-define <2 x i16> @test2() {
+define <2 x i16> @test2() null_pointer_is_valid {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    ret <2 x i16> <i16 ptrtoint (ptr getelementptr (i32, ptr null, i64 5) to i16), i16 ptrtoint (ptr getelementptr (i32, ptr null, i64 7) to i16)>