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[LLVM][CodeGen][AArch64] Don't scalarise v8{f16,bf16} vsetcc operations. #135398
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Original file line number | Diff line number | Diff line change |
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@@ -843,18 +843,21 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, | |
setOperationPromotedToType(ISD::FRINT, V4Narrow, MVT::v4f32); | ||
setOperationPromotedToType(ISD::FNEARBYINT, V4Narrow, MVT::v4f32); | ||
setOperationPromotedToType(ISD::FCANONICALIZE, V4Narrow, MVT::v4f32); | ||
setOperationPromotedToType(ISD::SETCC, V4Narrow, MVT::v4f32); | ||
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setOperationAction(ISD::FABS, V4Narrow, Legal); | ||
setOperationAction(ISD::FNEG, V4Narrow, Legal); | ||
setOperationAction(ISD::FNEG, V4Narrow, Legal); | ||
setOperationAction(ISD::FMA, V4Narrow, Expand); | ||
setOperationAction(ISD::SETCC, V4Narrow, Custom); | ||
setOperationAction(ISD::BR_CC, V4Narrow, Expand); | ||
setOperationAction(ISD::SELECT, V4Narrow, Expand); | ||
setOperationAction(ISD::SELECT_CC, V4Narrow, Expand); | ||
setOperationAction(ISD::FCOPYSIGN, V4Narrow, Custom); | ||
setOperationAction(ISD::FSQRT, V4Narrow, Expand); | ||
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auto V8Narrow = MVT::getVectorVT(ScalarVT, 8); | ||
setOperationPromotedToType(ISD::FCANONICALIZE, V8Narrow, MVT::v8f32); | ||
setOperationPromotedToType(ISD::SETCC, V8Narrow, MVT::v8f32); | ||
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setOperationAction(ISD::FABS, V8Narrow, Legal); | ||
setOperationAction(ISD::FADD, V8Narrow, Legal); | ||
setOperationAction(ISD::FCEIL, V8Narrow, Legal); | ||
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@@ -864,19 +867,17 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, | |
setOperationAction(ISD::FMA, V8Narrow, Expand); | ||
setOperationAction(ISD::FMUL, V8Narrow, Legal); | ||
setOperationAction(ISD::FNEARBYINT, V8Narrow, Legal); | ||
setOperationAction(ISD::FNEG, V8Narrow, Legal); | ||
setOperationAction(ISD::FNEG, V8Narrow, Legal); | ||
setOperationAction(ISD::FROUND, V8Narrow, Legal); | ||
setOperationAction(ISD::FROUNDEVEN, V8Narrow, Legal); | ||
setOperationAction(ISD::FRINT, V8Narrow, Legal); | ||
setOperationAction(ISD::FSQRT, V8Narrow, Expand); | ||
setOperationAction(ISD::FSUB, V8Narrow, Legal); | ||
setOperationAction(ISD::FTRUNC, V8Narrow, Legal); | ||
setOperationAction(ISD::SETCC, V8Narrow, Expand); | ||
setOperationAction(ISD::BR_CC, V8Narrow, Expand); | ||
setOperationAction(ISD::SELECT, V8Narrow, Expand); | ||
setOperationAction(ISD::SELECT_CC, V8Narrow, Expand); | ||
setOperationAction(ISD::FP_EXTEND, V8Narrow, Expand); | ||
setOperationPromotedToType(ISD::FCANONICALIZE, V8Narrow, MVT::v8f32); | ||
}; | ||
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if (!Subtarget->hasFullFP16()) { | ||
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@@ -15904,6 +15905,12 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op, | |
if (LHS.getValueType().getVectorElementType().isInteger()) | ||
return Op; | ||
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assert(((!Subtarget->hasFullFP16() && | ||
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LHS.getValueType().getVectorElementType() != MVT::f16) || | ||
LHS.getValueType().getVectorElementType() != MVT::bf16 || | ||
LHS.getValueType().getVectorElementType() != MVT::f128) && | ||
"Unexpected type!"); | ||
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// Lower isnan(x) | isnan(never-nan) to x != x. | ||
// Lower !isnan(x) & !isnan(never-nan) to x == x. | ||
if (CC == ISD::SETUO || CC == ISD::SETO) { | ||
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@@ -15922,26 +15929,6 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op, | |
} | ||
} | ||
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const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16(); | ||
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// Make v4f16 (only) fcmp operations utilise vector instructions | ||
// v8f16 support will be a litle more complicated | ||
if ((!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) || | ||
LHS.getValueType().getVectorElementType() == MVT::bf16) { | ||
if (LHS.getValueType().getVectorNumElements() == 4) { | ||
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS); | ||
RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS); | ||
SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC); | ||
DAG.ReplaceAllUsesWith(Op, NewSetcc); | ||
CmpVT = MVT::v4i32; | ||
} else | ||
return SDValue(); | ||
} | ||
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assert((!FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16) || | ||
LHS.getValueType().getVectorElementType() != MVT::bf16 || | ||
LHS.getValueType().getVectorElementType() != MVT::f128); | ||
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// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally | ||
// clean. Some of them require two branches to implement. | ||
AArch64CC::CondCode CC1, CC2; | ||
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I would expect this to just mark the node as promote. Do you know why this needs to provide the necessary vector type to promote to, and that isn't automatically handled by getTypeToPromoteTo?
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getTypeToPromoteTo
does not work in the natural way when operating on vector types. Specially, there is no guarantee the input and output element counts will match and indeed on AArch64getTypeToPromoteTo(v4f16)
returnsv2f32
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Sorry I missed this patch in other reviews and reviewers - my point was that perhaps it is better to get getTypeToPromoteTo to work for vectors too. It doesn't seem very useful to have the function never work and every target need to override half and bfloat vectors types. Something to think about at least, the patch looks good.
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Thanks, I'll add it to my TODO list to revisit. I have investigated this in the past and found uses that relied on the current behaviour. I recall things like using promotion to canonicalise all vector loads to integer vector loads. Perhaps I misunderstood the code back then or the compiler has simply moved on. Hopefully the latter because like you say the current default doesn't feel much like promotion.