[LoongArch] Don't crash on instruction prefetch intrinsics #135760
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Instead of failing to select during isel, drop the intrinsic in lowering. Similar as the X86's PR. Seeing: https://reviews.llvm.org/D151050. Fixes llvm#134624
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@llvm/pr-subscribers-backend-loongarch Author: None (leecheechen) ChangesInstead of failing to select during isel, drop the intrinsic in lowering. Similar as the X86's PR. Seeing: https://reviews.llvm.org/D151050. Fixes #134624 Full diff: https://github.com/llvm/llvm-project/pull/135760.diff 3 Files Affected:
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 002d88cbeeba3..44194b5829182 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -99,7 +99,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
+ setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
// Expand bitreverse.i16 with native-width bitrev and shift for now, before
// we get to know which of sll and revb.2h is faster.
@@ -465,10 +465,24 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
return lowerBITREVERSE(Op, DAG);
case ISD::SCALAR_TO_VECTOR:
return lowerSCALAR_TO_VECTOR(Op, DAG);
+ case ISD::PREFETCH:
+ return lowerPREFETCH(Op, DAG);
}
return SDValue();
}
+SDValue LoongArchTargetLowering::lowerPREFETCH(SDValue Op,
+ SelectionDAG &DAG) const {
+ unsigned IsData = Op.getConstantOperandVal(4);
+
+ // We don't support non-data prefetch.
+ // Just preserve the chain.
+ if (!IsData)
+ return Op.getOperand(0);
+
+ return Op;
+}
+
SDValue
LoongArchTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 52d88b9b24a6b..8c2d2597a26ec 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -353,6 +353,7 @@ class LoongArchTargetLowering : public TargetLowering {
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerBITREVERSE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
diff --git a/llvm/test/CodeGen/LoongArch/prefetchi.ll b/llvm/test/CodeGen/LoongArch/prefetchi.ll
new file mode 100644
index 0000000000000..a00f6f8161862
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/prefetchi.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind
+
+define dso_local void @prefetch_no_offset(ptr %ptr) nounwind {
+; LA32-LABEL: prefetch_no_offset:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ret
+;
+; LA64-LABEL: prefetch_no_offset:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ret
+entry:
+ tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 3, i32 0)
+ ret void
+}
+
+
+define dso_local void @prefetch_with_offset(ptr %ptr) nounwind {
+; LA32-LABEL: prefetch_with_offset:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ret
+;
+; LA64-LABEL: prefetch_with_offset:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ret
+entry:
+ %addr = getelementptr i8, ptr %ptr, i64 200
+ tail call void @llvm.prefetch(ptr %addr, i32 0, i32 3, i32 0)
+ ret void
+}
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heiher
approved these changes
Apr 16, 2025
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/59/builds/16107 Here is the relevant piece of the build log for the reference |
var-const
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Apr 17, 2025
Instead of failing to select during isel, drop the intrinsic in lowering. Similar as the X86's PR. Seeing: https://reviews.llvm.org/D151050. Fixes llvm#134624
swift-ci
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Apr 25, 2025
Instead of failing to select during isel, drop the intrinsic in lowering. Similar as the X86's PR. Seeing: https://reviews.llvm.org/D151050. Fixes llvm#134624 (cherry picked from commit dfb5b6e)
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Instead of failing to select during isel, drop the intrinsic in lowering.
Similar as the X86's PR. Seeing: https://reviews.llvm.org/D151050.
Fixes #134624