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[DAGCombiner] Disable narrowExtractedVectorLoad for indexed loads. #135847

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Merged
merged 1 commit into from
Apr 15, 2025
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[DAGCombiner] Disable narrowExtractedVectorLoad for indexed loads. #135847

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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -25183,7 +25183,7 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
return SDValue();

auto *Ld = dyn_cast<LoadSDNode>(Extract->getOperand(0));
if (!Ld || Ld->getExtensionType() || !Ld->isSimple())
if (!Ld || !ISD::isNormalLoad(Ld) || !Ld->isSimple())
return SDValue();

// Allow targets to opt-out.
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27 changes: 27 additions & 0 deletions llvm/test/CodeGen/AArch64/pr135821.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s

define <4 x float> @f(ptr %0) {
; CHECK-LABEL: f:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: ldr q1, [x0, #56]!
; CHECK-NEXT: ldr d0, [x0, #16]
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl use
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
%2 = getelementptr inbounds nuw i8, ptr %0, i64 56
%3 = load <6 x float>, ptr %2, align 4
%4 = shufflevector <6 x float> %3, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
tail call void @use(ptr %2)
ret <4 x float> %4
}

declare void @use(ptr)
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