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Merged
merged 15 commits into from
Apr 25, 2025
Merged

CodeGen: Add ISD::AssertNoFPClass #135946

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62e1163
CodeGen: Add ISD::AssertNoFPClass
wzssyqa Apr 16, 2025
e727de1
fix typo assernofpclass
wzssyqa Apr 18, 2025
1024b94
Add isKnownNeverNaN test
wzssyqa Apr 21, 2025
d77aef1
Mention operands
wzssyqa Apr 21, 2025
5d3aaac
Fix typo
wzssyqa Apr 21, 2025
b06150f
Fix AssertNoFPClass assert
wzssyqa Apr 21, 2025
062db54
Fix code styles
Apr 21, 2025
30e6ee0
Add Vector test case
wzssyqa Apr 21, 2025
6f83b72
Add DemandedElts
wzssyqa Apr 21, 2025
b10ba65
Use 32bit target
wzssyqa Apr 21, 2025
a37c8c7
Fix MERGE_VALUE cases
wzssyqa Apr 21, 2025
e6f85cb
Add aggregate tests with fmin
wzssyqa Apr 22, 2025
bd34a89
Fix comment
wzssyqa Apr 22, 2025
7e5f6b1
Add snan and qnan test cases
wzssyqa Apr 22, 2025
247746e
Test both array and struct
wzssyqa Apr 24, 2025
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9 changes: 9 additions & 0 deletions llvm/include/llvm/CodeGen/ISDOpcodes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,15 @@ enum NodeType {
/// poisoned the assertion will not be true for that value.
AssertAlign,

/// AssertNoFPClass - These nodes record if a register contains a float
/// value that is known to be not some type.
/// This node takes two operands. The first is the node that is known
/// never to be some float types; the second is a constant value with
/// the value of FPClassTest (casted to uint32_t).
/// NOTE: In case of the source value (or any vector element value) is
/// poisoned the assertion will not be true for that value.
AssertNoFPClass,

/// Various leaf nodes.
BasicBlock,
VALUETYPE,
Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/Target/TargetSelectionDAG.td
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Expand Up @@ -859,6 +859,7 @@ def SDT_assert : SDTypeProfile<1, 1,
[SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
def assertsext : SDNode<"ISD::AssertSext", SDT_assert>;
def assertzext : SDNode<"ISD::AssertZext", SDT_assert>;
def assertnofpclass : SDNode<"ISD::AssertNoFPClass", SDTFPUnaryOp>;
def assertalign : SDNode<"ISD::AssertAlign", SDT_assert>;

def convergencectrl_anchor : SDNode<"ISD::CONVERGENCECTRL_ANCHOR",
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Expand Up @@ -168,6 +168,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
case ISD::POISON:
case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N); break;
case ISD::VAARG: R = SoftenFloatRes_VAARG(N); break;
case ISD::AssertNoFPClass: R = GetSoftenedFloat(N->getOperand(0)); break;
case ISD::VECREDUCE_FADD:
case ISD::VECREDUCE_FMUL:
case ISD::VECREDUCE_FMIN:
Expand Down Expand Up @@ -2576,6 +2577,7 @@ bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
R = PromoteFloatOp_FAKE_USE(N, OpNo);
break;
case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
case ISD::AssertNoFPClass:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::LROUND:
Expand Down Expand Up @@ -2803,6 +2805,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FTRUNC:
case ISD::FTAN:
case ISD::FTANH:
case ISD::AssertNoFPClass:
case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break;

// Binary FP Operations
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Expand Up @@ -129,6 +129,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::UINT_TO_FP:
case ISD::ZERO_EXTEND:
case ISD::FCANONICALIZE:
case ISD::AssertNoFPClass:
R = ScalarizeVecRes_UnaryOp(N);
break;
case ISD::ADDRSPACECAST:
Expand Down Expand Up @@ -1276,6 +1277,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::UINT_TO_FP:
case ISD::VP_UINT_TO_FP:
case ISD::FCANONICALIZE:
case ISD::AssertNoFPClass:
SplitVecRes_UnaryOp(N, Lo, Hi);
break;
case ISD::ADDRSPACECAST:
Expand Down Expand Up @@ -4844,6 +4846,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FREEZE:
case ISD::ARITH_FENCE:
case ISD::FCANONICALIZE:
case ISD::AssertNoFPClass:
Res = WidenVecRes_Unary(N);
break;
case ISD::FMA: case ISD::VP_FMA:
Expand Down
19 changes: 19 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -5760,6 +5760,15 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, const APInt &DemandedElts,
return false;
return true;
}
case ISD::AssertNoFPClass: {
FPClassTest NoFPClass =
static_cast<FPClassTest>(Op.getConstantOperandVal(1));
if ((NoFPClass & fcNan) == fcNan)
return true;
if (SNaN && (NoFPClass & fcSNan) == fcSNan)
return true;
return isKnownNeverNaN(Op.getOperand(0), DemandedElts, SNaN, Depth + 1);
}
default:
if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) {
Expand Down Expand Up @@ -7406,6 +7415,16 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
N2.getOpcode() == ISD::TargetConstant && "Invalid FP_ROUND!");
if (N1.getValueType() == VT) return N1; // noop conversion.
break;
case ISD::AssertNoFPClass: {
assert(N1.getValueType().isFloatingPoint() &&
"AssertNoFPClass is used for a non-floating type");
assert(isa<ConstantSDNode>(N2) && "NoFPClass is not Constant");
FPClassTest NoFPClass = static_cast<FPClassTest>(N2->getAsZExtVal());
assert(llvm::to_underlying(NoFPClass) <=
BitmaskEnumDetail::Mask<FPClassTest>() &&
"FPClassTest value too large");
break;
}
case ISD::AssertSext:
case ISD::AssertZext: {
EVT EVT = cast<VTSDNode>(N2)->getVT();
Expand Down
15 changes: 12 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Expand Up @@ -11828,9 +11828,18 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
else if (Arg.hasAttribute(Attribute::ZExt))
AssertOp = ISD::AssertZext;

ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
PartVT, VT, nullptr, NewRoot,
F.getCallingConv(), AssertOp));
SDValue OutVal =
getCopyFromParts(DAG, dl, &InVals[i], NumParts, PartVT, VT, nullptr,
NewRoot, F.getCallingConv(), AssertOp);

FPClassTest NoFPClass = Arg.getNoFPClass();
if (NoFPClass != fcNone) {
SDValue SDNoFPClass = DAG.getTargetConstant(
static_cast<uint64_t>(NoFPClass), dl, MVT::i32);
OutVal = DAG.getNode(ISD::AssertNoFPClass, dl, OutVal.getValueType(),
OutVal, SDNoFPClass);
}
ArgValues.push_back(OutVal);
}

i += NumParts;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
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Expand Up @@ -122,6 +122,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::TokenFactor: return "TokenFactor";
case ISD::AssertSext: return "AssertSext";
case ISD::AssertZext: return "AssertZext";
case ISD::AssertNoFPClass: return "AssertNoFPClass";
case ISD::AssertAlign: return "AssertAlign";

case ISD::BasicBlock: return "BasicBlock";
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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Expand Up @@ -3265,6 +3265,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
return;
case ISD::AssertSext:
case ISD::AssertZext:
case ISD::AssertNoFPClass:
case ISD::AssertAlign:
ReplaceUses(SDValue(NodeToMatch, 0), NodeToMatch->getOperand(0));
CurDAG->RemoveDeadNode(NodeToMatch);
Expand Down
182 changes: 182 additions & 0 deletions llvm/test/CodeGen/AArch64/nofpclass.ll
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@@ -0,0 +1,182 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=aarch64-linux-gnu < %s | FileCheck %s

define float @f(float nofpclass(nan) %a, float nofpclass(nan) %b) {
; CHECK-LABEL: f:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmaxnm s0, s0, s1
; CHECK-NEXT: ret
entry:
%cond = tail call float @llvm.maximumnum.f32(float %a, float %b)
ret float %cond
}

define <4 x float> @fv4f32(<4 x float> nofpclass(nan) %a, <4 x float> nofpclass(nan) %b) {
; CHECK-LABEL: fv4f32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
entry:
%c = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %c
}

define {float, float} @m({float, float} nofpclass(nan) %a0, {float, float} nofpclass(nan) %a1) {
; CHECK-LABEL: m:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmaxnm s1, s1, s3
; CHECK-NEXT: fmaxnm s0, s0, s2
; CHECK-NEXT: ret
entry:
%a0f0 = extractvalue {float, float} %a0, 0
%a0f1 = extractvalue {float, float} %a0, 1
%a1f0 = extractvalue {float, float} %a1, 0
%a1f1 = extractvalue {float, float} %a1, 1
%max0 = tail call float @llvm.maximumnum.f32(float %a0f0, float %a1f0)
%max1 = tail call float @llvm.maximumnum.f32(float %a0f1, float %a1f1)
%ret0 = insertvalue {float, float} poison, float %max0, 0
%ret1 = insertvalue {float, float} %ret0, float %max1, 1
ret {float, float} %ret1
}

define [2 x float] @mA([2 x float] nofpclass(nan) %a0, [2 x float] nofpclass(nan) %a1) {
; CHECK-LABEL: mA:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmaxnm s1, s1, s3
; CHECK-NEXT: fmaxnm s0, s0, s2
; CHECK-NEXT: ret
entry:
%a0f0 = extractvalue [2 x float] %a0, 0
%a0f1 = extractvalue [2 x float] %a0, 1
%a1f0 = extractvalue [2 x float] %a1, 0
%a1f1 = extractvalue [2 x float] %a1, 1
%max0 = tail call float @llvm.maximumnum.f32(float %a0f0, float %a1f0)
%max1 = tail call float @llvm.maximumnum.f32(float %a0f1, float %a1f1)
%ret0 = insertvalue [2 x float] poison, float %max0, 0
%ret1 = insertvalue [2 x float] %ret0, float %max1, 1
ret [2 x float] %ret1
}

define float @fS(float nofpclass(snan) %a, float nofpclass(snan) %b) {
; CHECK-LABEL: fS:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmaxnm s0, s0, s1
; CHECK-NEXT: ret
entry:
%cond = tail call float @llvm.maximumnum.f32(float %a, float %b)
ret float %cond
}

define <4 x float> @fSv4f32(<4 x float> nofpclass(snan) %a, <4 x float> nofpclass(snan) %b) {
; CHECK-LABEL: fSv4f32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
entry:
%c = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %c
}

define {float, float} @mS({float, float} nofpclass(snan) %a0, {float, float} nofpclass(snan) %a1) {
; CHECK-LABEL: mS:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmaxnm s1, s1, s3
; CHECK-NEXT: fmaxnm s0, s0, s2
; CHECK-NEXT: ret
entry:
%a0f0 = extractvalue {float, float} %a0, 0
%a0f1 = extractvalue {float, float} %a0, 1
%a1f0 = extractvalue {float, float} %a1, 0
%a1f1 = extractvalue {float, float} %a1, 1
%max0 = tail call float @llvm.maximumnum.f32(float %a0f0, float %a1f0)
%max1 = tail call float @llvm.maximumnum.f32(float %a0f1, float %a1f1)
%ret0 = insertvalue {float, float} poison, float %max0, 0
%ret1 = insertvalue {float, float} %ret0, float %max1, 1
ret {float, float} %ret1
}

define [2 x float] @mAS([2 x float] nofpclass(snan) %a0, [2 x float] nofpclass(snan) %a1) {
; CHECK-LABEL: mAS:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmaxnm s1, s1, s3
; CHECK-NEXT: fmaxnm s0, s0, s2
; CHECK-NEXT: ret
entry:
%a0f0 = extractvalue [2 x float] %a0, 0
%a0f1 = extractvalue [2 x float] %a0, 1
%a1f0 = extractvalue [2 x float] %a1, 0
%a1f1 = extractvalue [2 x float] %a1, 1
%max0 = tail call float @llvm.maximumnum.f32(float %a0f0, float %a1f0)
%max1 = tail call float @llvm.maximumnum.f32(float %a0f1, float %a1f1)
%ret0 = insertvalue [2 x float] poison, float %max0, 0
%ret1 = insertvalue [2 x float] %ret0, float %max1, 1
ret [2 x float] %ret1
}

define float @fQ(float nofpclass(qnan) %a, float nofpclass(qnan) %b) {
; CHECK-LABEL: fQ:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fminnm s1, s1, s1
; CHECK-NEXT: fminnm s0, s0, s0
; CHECK-NEXT: fmaxnm s0, s0, s1
; CHECK-NEXT: ret
entry:
%cond = tail call float @llvm.maximumnum.f32(float %a, float %b)
ret float %cond
}

define <4 x float> @fQv4f32(<4 x float> nofpclass(qnan) %a, <4 x float> nofpclass(qnan) %b) {
; CHECK-LABEL: fQv4f32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fminnm v1.4s, v1.4s, v1.4s
; CHECK-NEXT: fminnm v0.4s, v0.4s, v0.4s
; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
entry:
%c = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %c
}

define {float, float} @mQ({float, float} nofpclass(qnan) %a0, {float, float} nofpclass(qnan) %a1) {
; CHECK-LABEL: mQ:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fminnm s2, s2, s2
; CHECK-NEXT: fminnm s0, s0, s0
; CHECK-NEXT: fminnm s3, s3, s3
; CHECK-NEXT: fminnm s1, s1, s1
; CHECK-NEXT: fmaxnm s0, s0, s2
; CHECK-NEXT: fmaxnm s1, s1, s3
; CHECK-NEXT: ret
entry:
%a0f0 = extractvalue {float, float} %a0, 0
%a0f1 = extractvalue {float, float} %a0, 1
%a1f0 = extractvalue {float, float} %a1, 0
%a1f1 = extractvalue {float, float} %a1, 1
%max0 = tail call float @llvm.maximumnum.f32(float %a0f0, float %a1f0)
%max1 = tail call float @llvm.maximumnum.f32(float %a0f1, float %a1f1)
%ret0 = insertvalue {float, float} poison, float %max0, 0
%ret1 = insertvalue {float, float} %ret0, float %max1, 1
ret {float, float} %ret1
}

define [2 x float] @mAQ([2 x float] nofpclass(qnan) %a0, [2 x float] nofpclass(qnan) %a1) {
; CHECK-LABEL: mAQ:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fminnm s2, s2, s2
; CHECK-NEXT: fminnm s0, s0, s0
; CHECK-NEXT: fminnm s3, s3, s3
; CHECK-NEXT: fminnm s1, s1, s1
; CHECK-NEXT: fmaxnm s0, s0, s2
; CHECK-NEXT: fmaxnm s1, s1, s3
; CHECK-NEXT: ret
entry:
%a0f0 = extractvalue [2 x float] %a0, 0
%a0f1 = extractvalue [2 x float] %a0, 1
%a1f0 = extractvalue [2 x float] %a1, 0
%a1f1 = extractvalue [2 x float] %a1, 1
%max0 = tail call float @llvm.maximumnum.f32(float %a0f0, float %a1f0)
%max1 = tail call float @llvm.maximumnum.f32(float %a0f1, float %a1f1)
%ret0 = insertvalue [2 x float] poison, float %max0, 0
%ret1 = insertvalue [2 x float] %ret0, float %max1, 1
ret [2 x float] %ret1
}
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