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[RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext #136287

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Merged
merged 2 commits into from
Apr 22, 2025
Merged

[RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext #136287

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bb6fe51
[RISCV] Pre-commit test
tclin914 Apr 18, 2025
cb71c3f
[RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext
tclin914 Apr 18, 2025
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4 changes: 3 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -653,7 +653,9 @@ bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
return false;

const unsigned Msb = ExtSize - 1;
const unsigned Lsb = RightShAmt;
// If the shift-right amount is greater than Msb, it means that extracts
// the X[Msb] bit and sign-extend it.
const unsigned Lsb = RightShAmt > Msb ? Msb : RightShAmt;

SDNode *TH_EXT = BitfieldExtract(N0, Msb, Lsb, DL, VT);
ReplaceNode(Node, TH_EXT);
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32 changes: 32 additions & 0 deletions llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
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Expand Up @@ -401,6 +401,38 @@ define i64 @no_sexth_i64(i64 %a) nounwind {
ret i64 %shr
}

define i32 @sext_sextinreg_sra(i16 %a) nounwind {
; RV32I-LABEL: sext_sextinreg_sra:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 26
; RV32I-NEXT: ret
;
; RV32XTHEADBB-LABEL: sext_sextinreg_sra:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: th.ext a0, a0, 15, 10
; RV32XTHEADBB-NEXT: ret
%sext = sext i16 %a to i32
%shr = ashr exact i32 %sext, 10
ret i32 %shr
}

define i32 @sext_sextinreg_sra_2(i16 %a) nounwind {
; RV32I-LABEL: sext_sextinreg_sra_2:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: ret
;
; RV32XTHEADBB-LABEL: sext_sextinreg_sra_2:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: th.ext a0, a0, 15, 15
; RV32XTHEADBB-NEXT: ret
%sext = sext i16 %a to i32
%shr = ashr exact i32 %sext, 24
ret i32 %shr
}

define i32 @zexth_i32(i32 %a) nounwind {
; RV32I-LABEL: zexth_i32:
; RV32I: # %bb.0:
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